Searched hist:"5071 f7c7ee0c1ef1498d71f6ac65e71014044498" (Results 1 – 5 of 5) sorted by relevance
| /rk3399_ARM-atf/plat/nxp/s32/s32g274ardb2/include/ |
| H A D | s32cc-ncore.h | 5071f7c7ee0c1ef1498d71f6ac65e71014044498 Wed Sep 25 11:03:33 UTC 2024 Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com> feat(s32g274a): add ncore support
Ncore is a cache-coherent interconnect module. It enables the
integration of heterogenous coherent agents and non-coherent
agents in a chip. TF-A boots with the first core in isolation
to avoid crashes due to cache invalidation operations. Later,
it will disable the isolation and reconfigure the module every
time a new core is added or removed through PSCI.
Change-Id: Ida42db91b10be1e66c3b9b73674d1e37a61844dd
Signed-off-by: Dan Nica <dan.nica@nxp.com>
Signed-off-by: Bogdan Hamciuc <bogdan.hamciuc@nxp.com>
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>
|
| /rk3399_ARM-atf/plat/nxp/s32/s32g274ardb2/ |
| H A D | s32cc_ncore.c | 5071f7c7ee0c1ef1498d71f6ac65e71014044498 Wed Sep 25 11:03:33 UTC 2024 Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com> feat(s32g274a): add ncore support
Ncore is a cache-coherent interconnect module. It enables the
integration of heterogenous coherent agents and non-coherent
agents in a chip. TF-A boots with the first core in isolation
to avoid crashes due to cache invalidation operations. Later,
it will disable the isolation and reconfigure the module every
time a new core is added or removed through PSCI.
Change-Id: Ida42db91b10be1e66c3b9b73674d1e37a61844dd
Signed-off-by: Dan Nica <dan.nica@nxp.com>
Signed-off-by: Bogdan Hamciuc <bogdan.hamciuc@nxp.com>
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>
|
| H A D | plat_helpers.S | 5071f7c7ee0c1ef1498d71f6ac65e71014044498 Wed Sep 25 11:03:33 UTC 2024 Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com> feat(s32g274a): add ncore support
Ncore is a cache-coherent interconnect module. It enables the
integration of heterogenous coherent agents and non-coherent
agents in a chip. TF-A boots with the first core in isolation
to avoid crashes due to cache invalidation operations. Later,
it will disable the isolation and reconfigure the module every
time a new core is added or removed through PSCI.
Change-Id: Ida42db91b10be1e66c3b9b73674d1e37a61844dd
Signed-off-by: Dan Nica <dan.nica@nxp.com>
Signed-off-by: Bogdan Hamciuc <bogdan.hamciuc@nxp.com>
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>
|
| H A D | plat_bl2_el3_setup.c | 5071f7c7ee0c1ef1498d71f6ac65e71014044498 Wed Sep 25 11:03:33 UTC 2024 Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com> feat(s32g274a): add ncore support
Ncore is a cache-coherent interconnect module. It enables the
integration of heterogenous coherent agents and non-coherent
agents in a chip. TF-A boots with the first core in isolation
to avoid crashes due to cache invalidation operations. Later,
it will disable the isolation and reconfigure the module every
time a new core is added or removed through PSCI.
Change-Id: Ida42db91b10be1e66c3b9b73674d1e37a61844dd
Signed-off-by: Dan Nica <dan.nica@nxp.com>
Signed-off-by: Bogdan Hamciuc <bogdan.hamciuc@nxp.com>
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>
|
| H A D | platform.mk | 5071f7c7ee0c1ef1498d71f6ac65e71014044498 Wed Sep 25 11:03:33 UTC 2024 Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com> feat(s32g274a): add ncore support
Ncore is a cache-coherent interconnect module. It enables the
integration of heterogenous coherent agents and non-coherent
agents in a chip. TF-A boots with the first core in isolation
to avoid crashes due to cache invalidation operations. Later,
it will disable the isolation and reconfigure the module every
time a new core is added or removed through PSCI.
Change-Id: Ida42db91b10be1e66c3b9b73674d1e37a61844dd
Signed-off-by: Dan Nica <dan.nica@nxp.com>
Signed-off-by: Bogdan Hamciuc <bogdan.hamciuc@nxp.com>
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>
|