1 /*
2 * Copyright 2024-2025 NXP
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7 #include <errno.h>
8
9 #include <common/debug.h>
10 #include <common/desc_image_load.h>
11 #include <drivers/generic_delay_timer.h>
12 #include <imx_usdhc.h>
13 #include <lib/mmio.h>
14 #include <lib/utils.h>
15 #include <lib/xlat_tables/xlat_tables_v2.h>
16 #include <plat/common/platform.h>
17 #include <plat_console.h>
18 #include <s32cc-clk-drv.h>
19
20 #include <plat_io_storage.h>
21 #include <s32cc-bl-common.h>
22 #include <s32cc-ncore.h>
23
24 #define SIUL20_BASE UL(0x4009C000)
25 #define SIUL2_PC09_MSCR UL(0x4009C2E4)
26 #define SIUL2_PC10_MSCR UL(0x4009C2E8)
27 #define SIUL2_PC10_LIN0_IMCR UL(0x4009CA40)
28
29 #define LIN0_TX_MSCR_CFG U(0x00214001)
30 #define LIN0_RX_MSCR_CFG U(0x00094000)
31 #define LIN0_RX_IMCR_CFG U(0x00000002)
32
plat_get_bl_image_load_info(void)33 struct bl_load_info *plat_get_bl_image_load_info(void)
34 {
35 return get_bl_load_info_from_mem_params_desc();
36 }
37
plat_get_next_bl_params(void)38 struct bl_params *plat_get_next_bl_params(void)
39 {
40 return get_next_bl_params_from_mem_params_desc();
41 }
42
plat_flush_next_bl_params(void)43 void plat_flush_next_bl_params(void)
44 {
45 flush_bl_params_desc();
46 }
47
bl2_platform_setup(void)48 void bl2_platform_setup(void)
49 {
50 int ret;
51
52 ret = mmap_add_dynamic_region(S32G_FIP_BASE, S32G_FIP_BASE,
53 S32G_FIP_SIZE,
54 MT_MEMORY | MT_RW | MT_SECURE);
55 if (ret != 0) {
56 panic();
57 }
58 }
59
s32g_mmap_siul2(void)60 static int s32g_mmap_siul2(void)
61 {
62 return mmap_add_dynamic_region(SIUL20_BASE, SIUL20_BASE, PAGE_SIZE,
63 MT_DEVICE | MT_RW | MT_SECURE);
64 }
65
linflex_config_pinctrl(void)66 static void linflex_config_pinctrl(void)
67 {
68 /* set PC09 - MSCR[41] - for UART0 TXD */
69 mmio_write_32(SIUL2_PC09_MSCR, LIN0_TX_MSCR_CFG);
70 /* set PC10 - MSCR[42] - for UART0 RXD */
71 mmio_write_32(SIUL2_PC10_MSCR, LIN0_RX_MSCR_CFG);
72 /* set PC10 - MSCR[512]/IMCR[0] - for UART0 RXD */
73 mmio_write_32(SIUL2_PC10_LIN0_IMCR, LIN0_RX_IMCR_CFG);
74 }
75
init_s32g_usdhc(void)76 static void init_s32g_usdhc(void)
77 {
78 static struct mmc_device_info sd_device_info = {
79 .mmc_dev_type = MMC_IS_SD_HC,
80 .ocr_voltage = OCR_3_2_3_3 | OCR_3_3_3_4,
81 };
82 imx_usdhc_params_t params;
83
84 zeromem(¶ms, sizeof(imx_usdhc_params_t));
85
86 params.reg_base = S32G_USDHC_BASE;
87 params.clk_rate = 25000000;
88 params.bus_width = MMC_BUS_WIDTH_4;
89 params.flags = MMC_FLAG_SD_CMD6;
90
91 imx_usdhc_init(¶ms, &sd_device_info);
92 }
93
plat_s32_mmc_setup(void)94 static void plat_s32_mmc_setup(void)
95 {
96 init_s32g_usdhc();
97 }
98
bl2_el3_early_platform_setup(u_register_t arg0,u_register_t arg1,u_register_t arg2,u_register_t arg3)99 void bl2_el3_early_platform_setup(u_register_t arg0, u_register_t arg1,
100 u_register_t arg2, u_register_t arg3)
101 {
102 int ret;
103
104 /* Restore (clear) the CAIUTC[IsolEn] bit for the primary cluster, which
105 * we have manually set during early BL2 boot.
106 */
107 ncore_disable_caiu_isolation(A53_CLUSTER0_CAIU);
108
109 ncore_init();
110 ncore_caiu_online(A53_CLUSTER0_CAIU);
111
112 ret = s32cc_init_core_clocks();
113 if (ret != 0) {
114 panic();
115 }
116
117 ret = s32cc_bl_mmu_setup();
118 if (ret != 0) {
119 panic();
120 }
121
122 ret = s32cc_init_early_clks();
123 if (ret != 0) {
124 panic();
125 }
126
127 ret = s32g_mmap_siul2();
128 if (ret != 0) {
129 panic();
130 }
131
132 generic_delay_timer_init();
133
134 /* Configure the generic timer frequency to ensure proper operation
135 * of the architectural timer in BL2.
136 */
137 write_cntfrq_el0(plat_get_syscnt_freq2());
138
139 linflex_config_pinctrl();
140 console_s32g2_register();
141
142 plat_s32_mmc_setup();
143
144 plat_s32g2_io_setup();
145 }
146
bl2_el3_plat_arch_setup(void)147 void bl2_el3_plat_arch_setup(void)
148 {
149 }
150
bl2_plat_handle_pre_image_load(unsigned int image_id)151 int bl2_plat_handle_pre_image_load(unsigned int image_id)
152 {
153 const struct bl_mem_params_node *desc = get_bl_mem_params_node(image_id);
154 const struct image_info *img_info;
155 size_t size;
156
157 if (desc == NULL) {
158 return -EINVAL;
159 }
160
161 img_info = &desc->image_info;
162
163 if ((img_info == NULL) || (img_info->image_max_size == 0U)) {
164 return -EINVAL;
165 }
166
167 size = page_align(img_info->image_max_size, UP);
168
169 return mmap_add_dynamic_region(img_info->image_base,
170 img_info->image_base,
171 size,
172 MT_MEMORY | MT_RW | MT_SECURE);
173 }
174