Searched hist:"46 f364fa0c611e96ef7f0d52e258ab4e38b4e9bb" (Results 1 – 4 of 4) sorted by relevance
| /rk3399_ARM-atf/include/lib/cpus/aarch64/ |
| H A D | cortex_a76ae.h | 46f364fa0c611e96ef7f0d52e258ab4e38b4e9bb Wed Nov 05 20:40:18 UTC 2025 Xialin Liu <xialin.liu@arm.com> fix(cpus): workaround for Cortex-A76AE erratum 1931427
Cortex-A76AE erratum 1931427 is a Cat B erratum that applies
to r0p0 and r1p0, it is fixed in r1p1.
This erratum can be avoided by setting CPUACTLR2_EL1[2] to 1. The bit
to force Atomic Store operations to write-back memory to be performed
in the L1 data cache.
SDEN documentation:
https://developer.arm.com/documentation/SDEN-1277541/1700/?lang=en
Change-Id: I31566838f894372e5627abda8b0bea1505f11f5d
Signed-off-by: Xialin Liu <xialin.liu@arm.com>
|
| /rk3399_ARM-atf/lib/cpus/aarch64/ |
| H A D | cortex_a76ae.S | 46f364fa0c611e96ef7f0d52e258ab4e38b4e9bb Wed Nov 05 20:40:18 UTC 2025 Xialin Liu <xialin.liu@arm.com> fix(cpus): workaround for Cortex-A76AE erratum 1931427
Cortex-A76AE erratum 1931427 is a Cat B erratum that applies
to r0p0 and r1p0, it is fixed in r1p1.
This erratum can be avoided by setting CPUACTLR2_EL1[2] to 1. The bit
to force Atomic Store operations to write-back memory to be performed
in the L1 data cache.
SDEN documentation:
https://developer.arm.com/documentation/SDEN-1277541/1700/?lang=en
Change-Id: I31566838f894372e5627abda8b0bea1505f11f5d
Signed-off-by: Xialin Liu <xialin.liu@arm.com>
|
| /rk3399_ARM-atf/docs/design/ |
| H A D | cpu-specific-build-macros.rst | 46f364fa0c611e96ef7f0d52e258ab4e38b4e9bb Wed Nov 05 20:40:18 UTC 2025 Xialin Liu <xialin.liu@arm.com> fix(cpus): workaround for Cortex-A76AE erratum 1931427
Cortex-A76AE erratum 1931427 is a Cat B erratum that applies
to r0p0 and r1p0, it is fixed in r1p1.
This erratum can be avoided by setting CPUACTLR2_EL1[2] to 1. The bit
to force Atomic Store operations to write-back memory to be performed
in the L1 data cache.
SDEN documentation:
https://developer.arm.com/documentation/SDEN-1277541/1700/?lang=en
Change-Id: I31566838f894372e5627abda8b0bea1505f11f5d
Signed-off-by: Xialin Liu <xialin.liu@arm.com>
|
| /rk3399_ARM-atf/lib/cpus/ |
| H A D | cpu-ops.mk | 46f364fa0c611e96ef7f0d52e258ab4e38b4e9bb Wed Nov 05 20:40:18 UTC 2025 Xialin Liu <xialin.liu@arm.com> fix(cpus): workaround for Cortex-A76AE erratum 1931427
Cortex-A76AE erratum 1931427 is a Cat B erratum that applies
to r0p0 and r1p0, it is fixed in r1p1.
This erratum can be avoided by setting CPUACTLR2_EL1[2] to 1. The bit
to force Atomic Store operations to write-back memory to be performed
in the L1 data cache.
SDEN documentation:
https://developer.arm.com/documentation/SDEN-1277541/1700/?lang=en
Change-Id: I31566838f894372e5627abda8b0bea1505f11f5d
Signed-off-by: Xialin Liu <xialin.liu@arm.com>
|