19ccc5a57SAlexei Fedorov /* 246f364faSXialin Liu * Copyright (c) 2019-2025, Arm Limited. All rights reserved. 39ccc5a57SAlexei Fedorov * 49ccc5a57SAlexei Fedorov * SPDX-License-Identifier: BSD-3-Clause 59ccc5a57SAlexei Fedorov */ 69ccc5a57SAlexei Fedorov 79ccc5a57SAlexei Fedorov #ifndef CORTEX_A76AE_H 89ccc5a57SAlexei Fedorov #define CORTEX_A76AE_H 99ccc5a57SAlexei Fedorov 109ccc5a57SAlexei Fedorov #include <lib/utils_def.h> 119ccc5a57SAlexei Fedorov 129ccc5a57SAlexei Fedorov /* Cortex-A76AE MIDR for revision 0 */ 139ccc5a57SAlexei Fedorov #define CORTEX_A76AE_MIDR U(0x410FD0E0) 149ccc5a57SAlexei Fedorov 155f802c88SBipin Ravi /* Cortex-A76 loop count for CVE-2022-23960 mitigation */ 165f802c88SBipin Ravi #define CORTEX_A76AE_BHB_LOOP_COUNT U(24) 175f802c88SBipin Ravi 189ccc5a57SAlexei Fedorov /******************************************************************************* 199ccc5a57SAlexei Fedorov * CPU Extended Control register specific definitions. 209ccc5a57SAlexei Fedorov ******************************************************************************/ 219ccc5a57SAlexei Fedorov #define CORTEX_A76AE_CPUPWRCTLR_EL1 S3_0_C15_C2_7 229ccc5a57SAlexei Fedorov 2346f364faSXialin Liu /******************************************************************************* 2446f364faSXialin Liu * CPU Auxiliary Control register specific definitions. 2546f364faSXialin Liu ******************************************************************************/ 2616de9faeSXialin Liu #define CORTEX_A76AE_CPUACTLR_EL1 S3_0_C15_C1_0 2746f364faSXialin Liu #define CORTEX_A76AE_CPUACTLR2_EL1 S3_0_C15_C1_1 2846f364faSXialin Liu 29*d428b422SXialin Liu /******************************************************************************* 30*d428b422SXialin Liu * CPU Private Control register specific definitions. 31*d428b422SXialin Liu ******************************************************************************/ 32*d428b422SXialin Liu #define CORTEX_A76AE_CPUPSELR_EL3 S3_6_c15_c8_0 33*d428b422SXialin Liu #define CORTEX_A76AE_CPUPCR_EL3 S3_6_c15_c8_1 34*d428b422SXialin Liu #define CORTEX_A76AE_CPUPOR_EL3 S3_6_c15_c8_2 35*d428b422SXialin Liu #define CORTEX_A76AE_CPUPMR_EL3 S3_6_c15_c8_3 36*d428b422SXialin Liu 379ccc5a57SAlexei Fedorov /* Definitions of register field mask in CORTEX_A76AE_CPUPWRCTLR_EL1 */ 389ccc5a57SAlexei Fedorov #define CORTEX_A76AE_CORE_PWRDN_EN_MASK U(0x1) 399ccc5a57SAlexei Fedorov 409ccc5a57SAlexei Fedorov #define CORTEX_A76AE_CPUECTLR_EL1 S3_0_C15_C1_4 419ccc5a57SAlexei Fedorov 429ccc5a57SAlexei Fedorov #endif /* CORTEX_A76AE_H */ 43