| #
14968c44 |
| 04-Dec-2025 |
Govindraj Raja <govindraj.raja@arm.com> |
Merge changes from topic "xl/a76ae-errata" into integration
* changes:
fix(cpus): workaround for Cortex-A76AE erratum 2371140
fix(cpus): workaround for Cortex-A76AE erratum 1969401
fix(cpus):
Merge changes from topic "xl/a76ae-errata" into integration
* changes:
fix(cpus): workaround for Cortex-A76AE erratum 2371140
fix(cpus): workaround for Cortex-A76AE erratum 1969401
fix(cpus): workaround for Cortex-A76AE erratum 1931435
fix(cpus): workaround for Cortex-A76AE erratum 1931427
show more ...
|
| #
d428b422 |
| 05-Nov-2025 |
Xialin Liu <xialin.liu@arm.com> |
fix(cpus): workaround for Cortex-A76AE erratum 1969401
Cortex-A76AE erratum 1969401 is a Cat B erratum that applies
to r0p0 and r1p0, it is fixed in r1p1.
This erratum can be avoided by inserting a
fix(cpus): workaround for Cortex-A76AE erratum 1969401
Cortex-A76AE erratum 1969401 is a Cat B erratum that applies
to r0p0 and r1p0, it is fixed in r1p1.
This erratum can be avoided by inserting a DMB ST before acquire
atomic instructions without release semantics.
SDEN documentation:
https://developer.arm.com/documentation/SDEN-1277541/1700/?lang=en
Change-Id: I893452450d430833e6c5a8e33a1e37b708218576
Signed-off-by: Xialin Liu <xialin.liu@arm.com>
show more ...
|
| #
16de9fae |
| 05-Nov-2025 |
Xialin Liu <xialin.liu@arm.com> |
fix(cpus): workaround for Cortex-A76AE erratum 1931435
Cortex-A76AE erratum 1931435 is a Cat B erratum that applies
to r0p0 and r1p0, it is fixed in r1p1.
This erratum can be avoided by setting CPU
fix(cpus): workaround for Cortex-A76AE erratum 1931435
Cortex-A76AE erratum 1931435 is a Cat B erratum that applies
to r0p0 and r1p0, it is fixed in r1p1.
This erratum can be avoided by setting CPUACTLR_EL1[13] to 1. This bit
delays instruction fetch after branch misprediction. This workaround
will have a small impact on performance.
SDEN documentation:
https://developer.arm.com/documentation/SDEN-1277541/1700/?lang=en
Change-Id: I1baba8752f5f2e2ab5c873030e1f00cbb8cf1e60
Signed-off-by: Xialin Liu <xialin.liu@arm.com>
show more ...
|
| #
46f364fa |
| 05-Nov-2025 |
Xialin Liu <xialin.liu@arm.com> |
fix(cpus): workaround for Cortex-A76AE erratum 1931427
Cortex-A76AE erratum 1931427 is a Cat B erratum that applies
to r0p0 and r1p0, it is fixed in r1p1.
This erratum can be avoided by setting CPU
fix(cpus): workaround for Cortex-A76AE erratum 1931427
Cortex-A76AE erratum 1931427 is a Cat B erratum that applies
to r0p0 and r1p0, it is fixed in r1p1.
This erratum can be avoided by setting CPUACTLR2_EL1[2] to 1. The bit
to force Atomic Store operations to write-back memory to be performed
in the L1 data cache.
SDEN documentation:
https://developer.arm.com/documentation/SDEN-1277541/1700/?lang=en
Change-Id: I31566838f894372e5627abda8b0bea1505f11f5d
Signed-off-by: Xialin Liu <xialin.liu@arm.com>
show more ...
|
| #
0a81a421 |
| 23-Mar-2022 |
Joanna Farley <joanna.farley@arm.com> |
Merge "fix(security): workaround for CVE-2022-23960 for A76AE, A78AE, A78C" into integration
|
| #
5f802c88 |
| 12-Mar-2022 |
Bipin Ravi <bipin.ravi@arm.com> |
fix(security): workaround for CVE-2022-23960 for A76AE, A78AE, A78C
Implements the loop workaround for Cortex-A76AE, Cortex-A78AE and
Cortex-A78C.
Signed-off-by: Bipin Ravi <bipin.ravi@arm.com>
Sig
fix(security): workaround for CVE-2022-23960 for A76AE, A78AE, A78C
Implements the loop workaround for Cortex-A76AE, Cortex-A78AE and
Cortex-A78C.
Signed-off-by: Bipin Ravi <bipin.ravi@arm.com>
Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>
Change-Id: I5c838f5b9d595ed3c461a7452bd465bd54acc548
show more ...
|
| #
01e7e0ca |
| 09-Apr-2019 |
Antonio Niño Díaz <antonio.ninodiaz@arm.com> |
Merge "Add support for Cortex-A76AE CPU" into integration
|
| #
9ccc5a57 |
| 04-Apr-2019 |
Alexei Fedorov <Alexei.Fedorov@arm.com> |
Add support for Cortex-A76AE CPU
Change-Id: I0a81f4ea94d41245cd5150de341b51fc70babffe
Signed-off-by: Alexei Fedorov <Alexei.Fedorov@arm.com>
|