"2b6051541b562b72d2cf784376a84552da18318d" (history) in projects: rk3399_rockchip-uboot

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Searched hist:"2 b6051541b562b72d2cf784376a84552da18318d" (Results 1 – 5 of 5) sorted by relevance

/rk3399_rockchip-uboot/doc/device-tree-bindings/misc/
H A D	intel-lpc.txt	`2b6051541b562b72d2cf784376a84552da18318d Thu Nov 13 05:42:15 UTC 2014 Simon Glass <sjg@chromium.org> x86: ivybridge: Add early LPC init so that serial works The PCH (Platform Controller Hub) includes an LPC (Low Pin Count) device which provides a serial port. This is accessible on Chromebooks, so enable it early in the boot process. Signed-off-by: Simon Glass <sjg@chromium.org>`
/rk3399_rockchip-uboot/arch/x86/include/asm/arch-ivybridge/
H A D	pch.h	`2b6051541b562b72d2cf784376a84552da18318d Thu Nov 13 05:42:15 UTC 2014 Simon Glass <sjg@chromium.org> x86: ivybridge: Add early LPC init so that serial works The PCH (Platform Controller Hub) includes an LPC (Low Pin Count) device which provides a serial port. This is accessible on Chromebooks, so enable it early in the boot process. Signed-off-by: Simon Glass <sjg@chromium.org>`
/rk3399_rockchip-uboot/arch/x86/cpu/ivybridge/
H A D	lpc.c	`2b6051541b562b72d2cf784376a84552da18318d Thu Nov 13 05:42:15 UTC 2014 Simon Glass <sjg@chromium.org> x86: ivybridge: Add early LPC init so that serial works The PCH (Platform Controller Hub) includes an LPC (Low Pin Count) device which provides a serial port. This is accessible on Chromebooks, so enable it early in the boot process. Signed-off-by: Simon Glass <sjg@chromium.org>`
H A D	Makefile	`2b6051541b562b72d2cf784376a84552da18318d Thu Nov 13 05:42:15 UTC 2014 Simon Glass <sjg@chromium.org> x86: ivybridge: Add early LPC init so that serial works The PCH (Platform Controller Hub) includes an LPC (Low Pin Count) device which provides a serial port. This is accessible on Chromebooks, so enable it early in the boot process. Signed-off-by: Simon Glass <sjg@chromium.org>`
H A D	cpu.c	`2b6051541b562b72d2cf784376a84552da18318d Thu Nov 13 05:42:15 UTC 2014 Simon Glass <sjg@chromium.org> x86: ivybridge: Add early LPC init so that serial works The PCH (Platform Controller Hub) includes an LPC (Low Pin Count) device which provides a serial port. This is accessible on Chromebooks, so enable it early in the boot process. Signed-off-by: Simon Glass <sjg@chromium.org>`