board_f: x86: Use checkcpu() for CPU init

At present we misuse print_cpuinfo() do so CPU init on x86. This is done
because it is the next available call after the console is enabled. But
several arc

board_f: x86: Use checkcpu() for CPU init

At present we misuse print_cpuinfo() do so CPU init on x86. This is done
because it is the next available call after the console is enabled. But
several arches use checkcpu() instead. Despite the horrible name (which
we can fix), it seems a better choice.

Adjust the various x86 CPU implementations to move their init code into
checkcpu() and use print_cpuinfo() only for printing CPU info.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Stefan Roese <sr@denx.de>

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x86: ivybridge: Add more debugging for failures

Add various debug() messages in places where errors occur. This aids with
debugging.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin M

x86: ivybridge: Add more debugging for failures

Add various debug() messages in places where errors occur. This aids with
debugging.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>

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x86: Add debugging when cpu_common_init() fails

Add a debug() at this point to help figure out what is wrong.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>

x86: Move common PCH code into a common place

The SATA indexed register write functions are common to several Intel PCHs.
Move this into a common location.

Signed-off-by: Simon Glass <sjg@chromium.

x86: Move common PCH code into a common place

The SATA indexed register write functions are common to several Intel PCHs.
Move this into a common location.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>

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x86: Move common CPU code to its own place

Some of the Intel CPU code is common to several Intel CPUs. Move it into a
common location along with required declarations.

Signed-off-by: Simon Glass <s

x86: Move common CPU code to its own place

Some of the Intel CPU code is common to several Intel CPUs. Move it into a
common location along with required declarations.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>

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x86: Create a common header for Intel register access

There are several blocks of registers that are accessed from all over the
code on Intel CPUs. These don't currently have their own driver and it

x86: Create a common header for Intel register access

There are several blocks of registers that are accessed from all over the
code on Intel CPUs. These don't currently have their own driver and it is
not clear whether having a driver makes sense.

An example is the Memory Controller Hub (MCH). We map it to a known location
on some Intel chips (mostly those without FSP - Firmware Support Package).

Add a new header file for these registers, and move MCH into it.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>

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x86: Move microcode code to a common location

This code is used on several Intel CPUs. Move it into a common location.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@

x86: Move microcode code to a common location

This code is used on several Intel CPUs. Move it into a common location.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>

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Merge git://git.denx.de/u-boot-dm

dm: Use uclass_first_device_err() where it is useful

Use this new function in places where it simplifies the code.

Signed-off-by: Simon Glass <sjg@chromium.org>

x86: ivybridge: Convert enable_usb_bar() to use DM PCI API

Convert this function over to use the driver model PCI API. In this case
we want to avoid using the real PCI devices since they have not ye

x86: ivybridge: Convert enable_usb_bar() to use DM PCI API

Convert this function over to use the driver model PCI API. In this case
we want to avoid using the real PCI devices since they have not yet been
probed. Instead, write directly to their PCI configuration address.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>

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x86: ivybridge: Use the I2C driver to perform SMbus init

Move the init code into the I2C driver.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Heiko Schocher <hs@denx.de>
Reviewed-by:

x86: ivybridge: Use the I2C driver to perform SMbus init

Move the init code into the I2C driver.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Heiko Schocher <hs@denx.de>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>

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x86: ivybridge: Do the SATA init before relocation

The SATA device needs to set itself up so that it appears correctly on the
PCI bus. The easiest way to do this is to set it up to probe before
relo

x86: ivybridge: Do the SATA init before relocation

The SATA device needs to set itself up so that it appears correctly on the
PCI bus. The easiest way to do this is to set it up to probe before
relocation. This can do the early setup.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>

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x86: ivybridge: Move GPIO init to the LPC init() method

This init can happen in the driver also. Move it.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>

x86: ivybridge: Move graphics init much later

We don't need to init the graphics controller so early. Move it alongside
the other graphics setup, just before we run the ROM.

Signed-off-by: Simon Gl

x86: ivybridge: Move graphics init much later

We don't need to init the graphics controller so early. Move it alongside
the other graphics setup, just before we run the ROM.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>

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x86: ivybridge: Probe the LPC in CPU init

We can drop the explicit probe of the PCH since the LPC is a child device
and this will happen automatically.

Signed-off-by: Simon Glass <sjg@chromium.org>

x86: ivybridge: Probe the LPC in CPU init

We can drop the explicit probe of the PCH since the LPC is a child device
and this will happen automatically.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>

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x86: ivybridge: Move northbridge init into the probe() method

Now that we have a proper driver for the nortbridge, set it up in by probing
it, and move the early init code into the probe() method.

x86: ivybridge: Move northbridge init into the probe() method

Now that we have a proper driver for the nortbridge, set it up in by probing
it, and move the early init code into the probe() method.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>

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x86: ivybridge: Rename bd82x6x_init()

Rename the existing bd82x6x_init() to bd82x6x_init_extra(). We will remove
this in a later patch.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bi

x86: ivybridge: Rename bd82x6x_init()

Rename the existing bd82x6x_init() to bd82x6x_init_extra(). We will remove
this in a later patch.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>

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x86: ivybridge: Move more init to the probe() function

Move SPI and port80 init to lpc_early_init(), called from the LPC's probe()
method.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by:

x86: ivybridge: Move more init to the probe() function

Move SPI and port80 init to lpc_early_init(), called from the LPC's probe()
method.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>

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x86: ivybridge: Move lpc_early_init() to probe()

Move this code to the LPC's probe() method so that it will happen
automatically when the LPC is probed before relocation.

Signed-off-by: Simon Glass

x86: ivybridge: Move lpc_early_init() to probe()

Move this code to the LPC's probe() method so that it will happen
automatically when the LPC is probed before relocation.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>

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x86: ivybridge: Set up the LPC device using driver model

Find the LPC device in arch_cpu_init_dm() as a first step to converting
this code to use driver model. Probing the LPC will probe its parent

x86: ivybridge: Set up the LPC device using driver model

Find the LPC device in arch_cpu_init_dm() as a first step to converting
this code to use driver model. Probing the LPC will probe its parent (the
PCH) automatically, so make sure that probing the PCH does nothing before
relocation.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>

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x86: Remove HAVE_ACPI_RESUME

These are currently dead codes. Until we have complete ACPI support,
we don't know if it works or not. Remove to avoid confusion.

Signed-off-by: Bin Meng <bmeng.cn@gmai

x86: Remove HAVE_ACPI_RESUME

These are currently dead codes. Until we have complete ACPI support,
we don't know if it works or not. Remove to avoid confusion.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>

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x86: Convert to use driver model timer

Convert all x86 boards to use driver model tsc timer.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>

Merge branch 'master' of git://git.denx.de/u-boot

Merge git://git.denx.de/u-boot-x86

x86: chromebook_link: Enable the debug UART

Add support for the debug UART on link. This is useful for early debugging.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn

x86: chromebook_link: Enable the debug UART

Add support for the debug UART on link. This is useful for early debugging.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>

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