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/rk3399_rockchip-uboot/board/armadeus/apf27/
H A Dfpga.c14cfc4f3735d9704cb6a630ef302be596d380684 Thu Mar 13 12:07:57 UTC 2014 Michal Simek <michal.simek@xilinx.com> fpga: xilinx: Simplify load/dump/info function handling

Connect FPGA version with appropriate operations
to remove huge switch-cases for every FPGA family.
Tested on Zynq. Spartan2/Spartan3/Virtex2 just compile test.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
/rk3399_rockchip-uboot/board/astro/mcf5373l/
H A Dfpga.c14cfc4f3735d9704cb6a630ef302be596d380684 Thu Mar 13 12:07:57 UTC 2014 Michal Simek <michal.simek@xilinx.com> fpga: xilinx: Simplify load/dump/info function handling

Connect FPGA version with appropriate operations
to remove huge switch-cases for every FPGA family.
Tested on Zynq. Spartan2/Spartan3/Virtex2 just compile test.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
/rk3399_rockchip-uboot/include/
H A Dvirtex2.h14cfc4f3735d9704cb6a630ef302be596d380684 Thu Mar 13 12:07:57 UTC 2014 Michal Simek <michal.simek@xilinx.com> fpga: xilinx: Simplify load/dump/info function handling

Connect FPGA version with appropriate operations
to remove huge switch-cases for every FPGA family.
Tested on Zynq. Spartan2/Spartan3/Virtex2 just compile test.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
H A Dzynqpl.h14cfc4f3735d9704cb6a630ef302be596d380684 Thu Mar 13 12:07:57 UTC 2014 Michal Simek <michal.simek@xilinx.com> fpga: xilinx: Simplify load/dump/info function handling

Connect FPGA version with appropriate operations
to remove huge switch-cases for every FPGA family.
Tested on Zynq. Spartan2/Spartan3/Virtex2 just compile test.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
H A Dspartan2.h14cfc4f3735d9704cb6a630ef302be596d380684 Thu Mar 13 12:07:57 UTC 2014 Michal Simek <michal.simek@xilinx.com> fpga: xilinx: Simplify load/dump/info function handling

Connect FPGA version with appropriate operations
to remove huge switch-cases for every FPGA family.
Tested on Zynq. Spartan2/Spartan3/Virtex2 just compile test.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
H A Dxilinx.h14cfc4f3735d9704cb6a630ef302be596d380684 Thu Mar 13 12:07:57 UTC 2014 Michal Simek <michal.simek@xilinx.com> fpga: xilinx: Simplify load/dump/info function handling

Connect FPGA version with appropriate operations
to remove huge switch-cases for every FPGA family.
Tested on Zynq. Spartan2/Spartan3/Virtex2 just compile test.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
H A Dspartan3.h14cfc4f3735d9704cb6a630ef302be596d380684 Thu Mar 13 12:07:57 UTC 2014 Michal Simek <michal.simek@xilinx.com> fpga: xilinx: Simplify load/dump/info function handling

Connect FPGA version with appropriate operations
to remove huge switch-cases for every FPGA family.
Tested on Zynq. Spartan2/Spartan3/Virtex2 just compile test.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
/rk3399_rockchip-uboot/drivers/fpga/
H A Dspartan2.c14cfc4f3735d9704cb6a630ef302be596d380684 Thu Mar 13 12:07:57 UTC 2014 Michal Simek <michal.simek@xilinx.com> fpga: xilinx: Simplify load/dump/info function handling

Connect FPGA version with appropriate operations
to remove huge switch-cases for every FPGA family.
Tested on Zynq. Spartan2/Spartan3/Virtex2 just compile test.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
H A Dvirtex2.c14cfc4f3735d9704cb6a630ef302be596d380684 Thu Mar 13 12:07:57 UTC 2014 Michal Simek <michal.simek@xilinx.com> fpga: xilinx: Simplify load/dump/info function handling

Connect FPGA version with appropriate operations
to remove huge switch-cases for every FPGA family.
Tested on Zynq. Spartan2/Spartan3/Virtex2 just compile test.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
H A Dspartan3.c14cfc4f3735d9704cb6a630ef302be596d380684 Thu Mar 13 12:07:57 UTC 2014 Michal Simek <michal.simek@xilinx.com> fpga: xilinx: Simplify load/dump/info function handling

Connect FPGA version with appropriate operations
to remove huge switch-cases for every FPGA family.
Tested on Zynq. Spartan2/Spartan3/Virtex2 just compile test.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
H A Dzynqpl.c14cfc4f3735d9704cb6a630ef302be596d380684 Thu Mar 13 12:07:57 UTC 2014 Michal Simek <michal.simek@xilinx.com> fpga: xilinx: Simplify load/dump/info function handling

Connect FPGA version with appropriate operations
to remove huge switch-cases for every FPGA family.
Tested on Zynq. Spartan2/Spartan3/Virtex2 just compile test.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
H A Dxilinx.c14cfc4f3735d9704cb6a630ef302be596d380684 Thu Mar 13 12:07:57 UTC 2014 Michal Simek <michal.simek@xilinx.com> fpga: xilinx: Simplify load/dump/info function handling

Connect FPGA version with appropriate operations
to remove huge switch-cases for every FPGA family.
Tested on Zynq. Spartan2/Spartan3/Virtex2 just compile test.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>