1d5dae85fSMichal Simek /* 2d5dae85fSMichal Simek * (C) Copyright 2012-2013, Xilinx, Michal Simek 3d5dae85fSMichal Simek * 4d5dae85fSMichal Simek * (C) Copyright 2012 5d5dae85fSMichal Simek * Joe Hershberger <joe.hershberger@ni.com> 6d5dae85fSMichal Simek * 71a459660SWolfgang Denk * SPDX-License-Identifier: GPL-2.0+ 8d5dae85fSMichal Simek */ 9d5dae85fSMichal Simek 10d5dae85fSMichal Simek #ifndef _ZYNQPL_H_ 11d5dae85fSMichal Simek #define _ZYNQPL_H_ 12d5dae85fSMichal Simek 13d5dae85fSMichal Simek #include <xilinx.h> 14d5dae85fSMichal Simek 15345f9e19SMichal Simek #if defined(CONFIG_FPGA_ZYNQPL) 1614cfc4f3SMichal Simek extern struct xilinx_fpga_op zynq_op; 17345f9e19SMichal Simek # define FPGA_ZYNQPL_OPS &zynq_op 18345f9e19SMichal Simek #else 19345f9e19SMichal Simek # define FPGA_ZYNQPL_OPS NULL 20345f9e19SMichal Simek #endif 21d5dae85fSMichal Simek 22*05c59d0bSMichal Simek #define XILINX_ZYNQ_7007S 0x3 23d5dae85fSMichal Simek #define XILINX_ZYNQ_7010 0x2 24*05c59d0bSMichal Simek #define XILINX_ZYNQ_7012S 0x1c 25*05c59d0bSMichal Simek #define XILINX_ZYNQ_7014S 0x8 2631993d6aSMichal Simek #define XILINX_ZYNQ_7015 0x1b 27d5dae85fSMichal Simek #define XILINX_ZYNQ_7020 0x7 28d5dae85fSMichal Simek #define XILINX_ZYNQ_7030 0xc 29b9103809SSiva Durga Prasad Paladugu #define XILINX_ZYNQ_7035 0x12 30d5dae85fSMichal Simek #define XILINX_ZYNQ_7045 0x11 31fd2b10b6SMichal Simek #define XILINX_ZYNQ_7100 0x16 32d5dae85fSMichal Simek 33d5dae85fSMichal Simek /* Device Image Sizes */ 34*05c59d0bSMichal Simek #define XILINX_XC7Z007S_SIZE 16669920/8 35d5dae85fSMichal Simek #define XILINX_XC7Z010_SIZE 16669920/8 36*05c59d0bSMichal Simek #define XILINX_XC7Z012S_SIZE 28085344/8 37*05c59d0bSMichal Simek #define XILINX_XC7Z014S_SIZE 32364512/8 3831993d6aSMichal Simek #define XILINX_XC7Z015_SIZE 28085344/8 39d5dae85fSMichal Simek #define XILINX_XC7Z020_SIZE 32364512/8 40d5dae85fSMichal Simek #define XILINX_XC7Z030_SIZE 47839328/8 41b9103809SSiva Durga Prasad Paladugu #define XILINX_XC7Z035_SIZE 106571232/8 42d5dae85fSMichal Simek #define XILINX_XC7Z045_SIZE 106571232/8 43fd2b10b6SMichal Simek #define XILINX_XC7Z100_SIZE 139330784/8 44d5dae85fSMichal Simek 45d5dae85fSMichal Simek /* Descriptor Macros */ 46*05c59d0bSMichal Simek #define XILINX_XC7Z007S_DESC(cookie) \ 47*05c59d0bSMichal Simek { xilinx_zynq, devcfg, XILINX_XC7Z007S_SIZE, NULL, cookie, FPGA_ZYNQPL_OPS, \ 48*05c59d0bSMichal Simek "7z007s" } 49*05c59d0bSMichal Simek 50d5dae85fSMichal Simek #define XILINX_XC7Z010_DESC(cookie) \ 51345f9e19SMichal Simek { xilinx_zynq, devcfg, XILINX_XC7Z010_SIZE, NULL, cookie, FPGA_ZYNQPL_OPS, \ 52345f9e19SMichal Simek "7z010" } 53d5dae85fSMichal Simek 54*05c59d0bSMichal Simek #define XILINX_XC7Z012S_DESC(cookie) \ 55*05c59d0bSMichal Simek { xilinx_zynq, devcfg, XILINX_XC7Z012S_SIZE, NULL, cookie, FPGA_ZYNQPL_OPS, \ 56*05c59d0bSMichal Simek "7z012s" } 57*05c59d0bSMichal Simek 58*05c59d0bSMichal Simek #define XILINX_XC7Z014S_DESC(cookie) \ 59*05c59d0bSMichal Simek { xilinx_zynq, devcfg, XILINX_XC7Z014S_SIZE, NULL, cookie, FPGA_ZYNQPL_OPS, \ 60*05c59d0bSMichal Simek "7z014s" } 61*05c59d0bSMichal Simek 6231993d6aSMichal Simek #define XILINX_XC7Z015_DESC(cookie) \ 63345f9e19SMichal Simek { xilinx_zynq, devcfg, XILINX_XC7Z015_SIZE, NULL, cookie, FPGA_ZYNQPL_OPS, \ 64345f9e19SMichal Simek "7z015" } 6531993d6aSMichal Simek 66d5dae85fSMichal Simek #define XILINX_XC7Z020_DESC(cookie) \ 67345f9e19SMichal Simek { xilinx_zynq, devcfg, XILINX_XC7Z020_SIZE, NULL, cookie, FPGA_ZYNQPL_OPS, \ 68345f9e19SMichal Simek "7z020" } 69d5dae85fSMichal Simek 70d5dae85fSMichal Simek #define XILINX_XC7Z030_DESC(cookie) \ 71345f9e19SMichal Simek { xilinx_zynq, devcfg, XILINX_XC7Z030_SIZE, NULL, cookie, FPGA_ZYNQPL_OPS, \ 72345f9e19SMichal Simek "7z030" } 73d5dae85fSMichal Simek 74b9103809SSiva Durga Prasad Paladugu #define XILINX_XC7Z035_DESC(cookie) \ 75b9103809SSiva Durga Prasad Paladugu { xilinx_zynq, devcfg, XILINX_XC7Z035_SIZE, NULL, cookie, FPGA_ZYNQPL_OPS, \ 76b9103809SSiva Durga Prasad Paladugu "7z035" } 77b9103809SSiva Durga Prasad Paladugu 78d5dae85fSMichal Simek #define XILINX_XC7Z045_DESC(cookie) \ 79345f9e19SMichal Simek { xilinx_zynq, devcfg, XILINX_XC7Z045_SIZE, NULL, cookie, FPGA_ZYNQPL_OPS, \ 80345f9e19SMichal Simek "7z045" } 81d5dae85fSMichal Simek 82fd2b10b6SMichal Simek #define XILINX_XC7Z100_DESC(cookie) \ 83345f9e19SMichal Simek { xilinx_zynq, devcfg, XILINX_XC7Z100_SIZE, NULL, cookie, FPGA_ZYNQPL_OPS, \ 84345f9e19SMichal Simek "7z100" } 85fd2b10b6SMichal Simek 86d5dae85fSMichal Simek #endif /* _ZYNQPL_H_ */ 87