1875c7893SWolfgang Denk /* 2875c7893SWolfgang Denk * (C) Copyright 2002 3875c7893SWolfgang Denk * Rich Ireland, Enterasys Networks, rireland@enterasys.com. 4875c7893SWolfgang Denk * 51a459660SWolfgang Denk * SPDX-License-Identifier: GPL-2.0+ 6875c7893SWolfgang Denk */ 7875c7893SWolfgang Denk 8875c7893SWolfgang Denk #ifndef _SPARTAN3_H_ 9875c7893SWolfgang Denk #define _SPARTAN3_H_ 10875c7893SWolfgang Denk 11875c7893SWolfgang Denk #include <xilinx.h> 12875c7893SWolfgang Denk 13875c7893SWolfgang Denk /* Slave Parallel Implementation function table */ 14875c7893SWolfgang Denk typedef struct { 152df9d5c4SMichal Simek xilinx_pre_fn pre; 162df9d5c4SMichal Simek xilinx_pgm_fn pgm; 172df9d5c4SMichal Simek xilinx_init_fn init; 182df9d5c4SMichal Simek xilinx_err_fn err; 192df9d5c4SMichal Simek xilinx_done_fn done; 202df9d5c4SMichal Simek xilinx_clk_fn clk; 212df9d5c4SMichal Simek xilinx_cs_fn cs; 222df9d5c4SMichal Simek xilinx_wr_fn wr; 232df9d5c4SMichal Simek xilinx_rdata_fn rdata; 242df9d5c4SMichal Simek xilinx_wdata_fn wdata; 252df9d5c4SMichal Simek xilinx_busy_fn busy; 262df9d5c4SMichal Simek xilinx_abort_fn abort; 272df9d5c4SMichal Simek xilinx_post_fn post; 282a6e3869SMichal Simek } xilinx_spartan3_slave_parallel_fns; 29875c7893SWolfgang Denk 30875c7893SWolfgang Denk /* Slave Serial Implementation function table */ 31875c7893SWolfgang Denk typedef struct { 322df9d5c4SMichal Simek xilinx_pre_fn pre; 332df9d5c4SMichal Simek xilinx_pgm_fn pgm; 342df9d5c4SMichal Simek xilinx_clk_fn clk; 352df9d5c4SMichal Simek xilinx_init_fn init; 362df9d5c4SMichal Simek xilinx_done_fn done; 372df9d5c4SMichal Simek xilinx_wr_fn wr; 382df9d5c4SMichal Simek xilinx_post_fn post; 392df9d5c4SMichal Simek xilinx_bwr_fn bwr; /* block write function */ 402df9d5c4SMichal Simek xilinx_abort_fn abort; 412a6e3869SMichal Simek } xilinx_spartan3_slave_serial_fns; 42875c7893SWolfgang Denk 43*a99a06cbSMichal Simek #if defined(CONFIG_FPGA_SPARTAN3) 4414cfc4f3SMichal Simek extern struct xilinx_fpga_op spartan3_op; 45*a99a06cbSMichal Simek # define FPGA_SPARTAN3_OPS &spartan3_op 46*a99a06cbSMichal Simek #else 47*a99a06cbSMichal Simek # define FPGA_SPARTAN3_OPS NULL 48*a99a06cbSMichal Simek #endif 4914cfc4f3SMichal Simek 50875c7893SWolfgang Denk /* Device Image Sizes 51875c7893SWolfgang Denk *********************************************************************/ 52875c7893SWolfgang Denk /* Spartan-III (1.2V) */ 53875c7893SWolfgang Denk #define XILINX_XC3S50_SIZE 439264/8 54875c7893SWolfgang Denk #define XILINX_XC3S200_SIZE 1047616/8 55875c7893SWolfgang Denk #define XILINX_XC3S400_SIZE 1699136/8 56875c7893SWolfgang Denk #define XILINX_XC3S1000_SIZE 3223488/8 57875c7893SWolfgang Denk #define XILINX_XC3S1500_SIZE 5214784/8 58875c7893SWolfgang Denk #define XILINX_XC3S2000_SIZE 7673024/8 59875c7893SWolfgang Denk #define XILINX_XC3S4000_SIZE 11316864/8 60875c7893SWolfgang Denk #define XILINX_XC3S5000_SIZE 13271936/8 61875c7893SWolfgang Denk 62923efd28SBruce Adler /* Spartan-3E (v3.4) */ 63923efd28SBruce Adler #define XILINX_XC3S100E_SIZE 581344/8 64923efd28SBruce Adler #define XILINX_XC3S250E_SIZE 1353728/8 65923efd28SBruce Adler #define XILINX_XC3S500E_SIZE 2270208/8 66923efd28SBruce Adler #define XILINX_XC3S1200E_SIZE 3841184/8 67923efd28SBruce Adler #define XILINX_XC3S1600E_SIZE 5969696/8 68923efd28SBruce Adler 6928cdc1c8SStefano Babic /* 7028cdc1c8SStefano Babic * Spartan-6 : the Spartan-6 family can be programmed 7128cdc1c8SStefano Babic * exactly as the Spartan-3 7228cdc1c8SStefano Babic */ 7328cdc1c8SStefano Babic #define XILINK_XC6SLX4_SIZE (3713568/8) 7428cdc1c8SStefano Babic 75875c7893SWolfgang Denk /* Descriptor Macros 76875c7893SWolfgang Denk *********************************************************************/ 773bff4ffaSMatthias Fuchs /* Spartan-III devices */ 78875c7893SWolfgang Denk #define XILINX_XC3S50_DESC(iface, fn_table, cookie) \ 79*a99a06cbSMichal Simek { xilinx_spartan3, iface, XILINX_XC3S50_SIZE, fn_table, cookie, \ 80*a99a06cbSMichal Simek FPGA_SPARTAN3_OPS } 81875c7893SWolfgang Denk 82875c7893SWolfgang Denk #define XILINX_XC3S200_DESC(iface, fn_table, cookie) \ 83*a99a06cbSMichal Simek { xilinx_spartan3, iface, XILINX_XC3S200_SIZE, fn_table, cookie, \ 84*a99a06cbSMichal Simek FPGA_SPARTAN3_OPS } 85875c7893SWolfgang Denk 86875c7893SWolfgang Denk #define XILINX_XC3S400_DESC(iface, fn_table, cookie) \ 87*a99a06cbSMichal Simek { xilinx_spartan3, iface, XILINX_XC3S400_SIZE, fn_table, cookie, \ 88*a99a06cbSMichal Simek FPGA_SPARTAN3_OPS } 89875c7893SWolfgang Denk 90875c7893SWolfgang Denk #define XILINX_XC3S1000_DESC(iface, fn_table, cookie) \ 91*a99a06cbSMichal Simek { xilinx_spartan3, iface, XILINX_XC3S1000_SIZE, fn_table, cookie, \ 92*a99a06cbSMichal Simek FPGA_SPARTAN3_OPS } 93875c7893SWolfgang Denk 94875c7893SWolfgang Denk #define XILINX_XC3S1500_DESC(iface, fn_table, cookie) \ 95*a99a06cbSMichal Simek { xilinx_spartan3, iface, XILINX_XC3S1500_SIZE, fn_table, cookie, \ 96*a99a06cbSMichal Simek FPGA_SPARTAN3_OPS } 97875c7893SWolfgang Denk 98875c7893SWolfgang Denk #define XILINX_XC3S2000_DESC(iface, fn_table, cookie) \ 99*a99a06cbSMichal Simek { xilinx_spartan3, iface, XILINX_XC3S2000_SIZE, fn_table, cookie, \ 100*a99a06cbSMichal Simek FPGA_SPARTAN3_OPS } 101875c7893SWolfgang Denk 102875c7893SWolfgang Denk #define XILINX_XC3S4000_DESC(iface, fn_table, cookie) \ 103*a99a06cbSMichal Simek { xilinx_spartan3, iface, XILINX_XC3S4000_SIZE, fn_table, cookie, \ 104*a99a06cbSMichal Simek FPGA_SPARTAN3_OPS } 105875c7893SWolfgang Denk 106875c7893SWolfgang Denk #define XILINX_XC3S5000_DESC(iface, fn_table, cookie) \ 107*a99a06cbSMichal Simek { xilinx_spartan3, iface, XILINX_XC3S5000_SIZE, fn_table, cookie, \ 108*a99a06cbSMichal Simek FPGA_SPARTAN3_OPS } 109875c7893SWolfgang Denk 110923efd28SBruce Adler /* Spartan-3E devices */ 111923efd28SBruce Adler #define XILINX_XC3S100E_DESC(iface, fn_table, cookie) \ 112*a99a06cbSMichal Simek { xilinx_spartan3, iface, XILINX_XC3S100E_SIZE, fn_table, cookie, \ 113*a99a06cbSMichal Simek FPGA_SPARTAN3_OPS } 114923efd28SBruce Adler 115923efd28SBruce Adler #define XILINX_XC3S250E_DESC(iface, fn_table, cookie) \ 116*a99a06cbSMichal Simek { xilinx_spartan3, iface, XILINX_XC3S250E_SIZE, fn_table, cookie, \ 117*a99a06cbSMichal Simek FPGA_SPARTAN3_OPS } 118923efd28SBruce Adler 119923efd28SBruce Adler #define XILINX_XC3S500E_DESC(iface, fn_table, cookie) \ 120*a99a06cbSMichal Simek { xilinx_spartan3, iface, XILINX_XC3S500E_SIZE, fn_table, cookie, \ 121*a99a06cbSMichal Simek FPGA_SPARTAN3_OPS } 122923efd28SBruce Adler 123923efd28SBruce Adler #define XILINX_XC3S1200E_DESC(iface, fn_table, cookie) \ 12414cfc4f3SMichal Simek { xilinx_spartan3, iface, XILINX_XC3S1200E_SIZE, fn_table, cookie, \ 125*a99a06cbSMichal Simek FPGA_SPARTAN3_OPS } 126923efd28SBruce Adler 127923efd28SBruce Adler #define XILINX_XC3S1600E_DESC(iface, fn_table, cookie) \ 12814cfc4f3SMichal Simek { xilinx_spartan3, iface, XILINX_XC3S1600E_SIZE, fn_table, cookie, \ 129*a99a06cbSMichal Simek FPGA_SPARTAN3_OPS } 130923efd28SBruce Adler 13128cdc1c8SStefano Babic #define XILINX_XC6SLX4_DESC(iface, fn_table, cookie) \ 132*a99a06cbSMichal Simek { xilinx_spartan3, iface, XILINK_XC6SLX4_SIZE, fn_table, cookie, \ 133*a99a06cbSMichal Simek FPGA_SPARTAN3_OPS } 13428cdc1c8SStefano Babic 135875c7893SWolfgang Denk #endif /* _SPARTAN3_H_ */ 136