1c609719bSwdenk /* 2c609719bSwdenk * (C) Copyright 2002 3c609719bSwdenk * Rich Ireland, Enterasys Networks, rireland@enterasys.com. 4c609719bSwdenk * 51a459660SWolfgang Denk * SPDX-License-Identifier: GPL-2.0+ 6c609719bSwdenk */ 7c609719bSwdenk 8c609719bSwdenk #ifndef _SPARTAN2_H_ 9c609719bSwdenk #define _SPARTAN2_H_ 10c609719bSwdenk 11c609719bSwdenk #include <xilinx.h> 12c609719bSwdenk 13c609719bSwdenk /* Slave Parallel Implementation function table */ 14c609719bSwdenk typedef struct { 152df9d5c4SMichal Simek xilinx_pre_fn pre; 162df9d5c4SMichal Simek xilinx_pgm_fn pgm; 172df9d5c4SMichal Simek xilinx_init_fn init; 182df9d5c4SMichal Simek xilinx_err_fn err; 192df9d5c4SMichal Simek xilinx_done_fn done; 202df9d5c4SMichal Simek xilinx_clk_fn clk; 212df9d5c4SMichal Simek xilinx_cs_fn cs; 222df9d5c4SMichal Simek xilinx_wr_fn wr; 232df9d5c4SMichal Simek xilinx_rdata_fn rdata; 242df9d5c4SMichal Simek xilinx_wdata_fn wdata; 252df9d5c4SMichal Simek xilinx_busy_fn busy; 262df9d5c4SMichal Simek xilinx_abort_fn abort; 272df9d5c4SMichal Simek xilinx_post_fn post; 28b625b9aeSMichal Simek } xilinx_spartan2_slave_parallel_fns; 29c609719bSwdenk 30c609719bSwdenk /* Slave Serial Implementation function table */ 31c609719bSwdenk typedef struct { 322df9d5c4SMichal Simek xilinx_pre_fn pre; 332df9d5c4SMichal Simek xilinx_pgm_fn pgm; 342df9d5c4SMichal Simek xilinx_clk_fn clk; 352df9d5c4SMichal Simek xilinx_init_fn init; 362df9d5c4SMichal Simek xilinx_done_fn done; 372df9d5c4SMichal Simek xilinx_wr_fn wr; 382df9d5c4SMichal Simek xilinx_post_fn post; 39b625b9aeSMichal Simek } xilinx_spartan2_slave_serial_fns; 40c609719bSwdenk 41*4e9acc16SMichal Simek #if defined(CONFIG_FPGA_SPARTAN2) 4214cfc4f3SMichal Simek extern struct xilinx_fpga_op spartan2_op; 43*4e9acc16SMichal Simek # define FPGA_SPARTAN2_OPS &spartan2_op 44*4e9acc16SMichal Simek #else 45*4e9acc16SMichal Simek # define FPGA_SPARTAN2_OPS NULL 46*4e9acc16SMichal Simek #endif 4714cfc4f3SMichal Simek 48c609719bSwdenk /* Device Image Sizes 49c609719bSwdenk *********************************************************************/ 50c609719bSwdenk /* Spartan-II (2.5V) */ 51c609719bSwdenk #define XILINX_XC2S15_SIZE 197728/8 52c609719bSwdenk #define XILINX_XC2S30_SIZE 336800/8 53c609719bSwdenk #define XILINX_XC2S50_SIZE 559232/8 54c609719bSwdenk #define XILINX_XC2S100_SIZE 781248/8 55c609719bSwdenk #define XILINX_XC2S150_SIZE 1040128/8 563bff4ffaSMatthias Fuchs #define XILINX_XC2S200_SIZE 1335872/8 57c609719bSwdenk 589dd611b8Swdenk /* Spartan-IIE (1.8V) */ 599dd611b8Swdenk #define XILINX_XC2S50E_SIZE 630048/8 609dd611b8Swdenk #define XILINX_XC2S100E_SIZE 863840/8 619dd611b8Swdenk #define XILINX_XC2S150E_SIZE 1134496/8 629dd611b8Swdenk #define XILINX_XC2S200E_SIZE 1442016/8 639dd611b8Swdenk #define XILINX_XC2S300E_SIZE 1875648/8 649dd611b8Swdenk 65c609719bSwdenk /* Descriptor Macros 66c609719bSwdenk *********************************************************************/ 67c609719bSwdenk /* Spartan-II devices */ 68c609719bSwdenk #define XILINX_XC2S15_DESC(iface, fn_table, cookie) \ 69*4e9acc16SMichal Simek { xilinx_spartan2, iface, XILINX_XC2S15_SIZE, fn_table, cookie, \ 70*4e9acc16SMichal Simek FPGA_SPARTAN2_OPS } 71c609719bSwdenk 72c609719bSwdenk #define XILINX_XC2S30_DESC(iface, fn_table, cookie) \ 73*4e9acc16SMichal Simek { xilinx_spartan2, iface, XILINX_XC2S30_SIZE, fn_table, cookie, \ 74*4e9acc16SMichal Simek FPGA_SPARTAN2_OPS } 75c609719bSwdenk 76c609719bSwdenk #define XILINX_XC2S50_DESC(iface, fn_table, cookie) \ 77*4e9acc16SMichal Simek { xilinx_spartan2, iface, XILINX_XC2S50_SIZE, fn_table, cookie, \ 78*4e9acc16SMichal Simek FPGA_SPARTAN2_OPS } 79c609719bSwdenk 80c609719bSwdenk #define XILINX_XC2S100_DESC(iface, fn_table, cookie) \ 81*4e9acc16SMichal Simek { xilinx_spartan2, iface, XILINX_XC2S100_SIZE, fn_table, cookie, \ 82*4e9acc16SMichal Simek FPGA_SPARTAN2_OPS } 83c609719bSwdenk 84c609719bSwdenk #define XILINX_XC2S150_DESC(iface, fn_table, cookie) \ 85*4e9acc16SMichal Simek { xilinx_spartan2, iface, XILINX_XC2S150_SIZE, fn_table, cookie, \ 86*4e9acc16SMichal Simek FPGA_SPARTAN2_OPS } 87c609719bSwdenk 883bff4ffaSMatthias Fuchs #define XILINX_XC2S200_DESC(iface, fn_table, cookie) \ 89*4e9acc16SMichal Simek { xilinx_spartan2, iface, XILINX_XC2S200_SIZE, fn_table, cookie, \ 90*4e9acc16SMichal Simek FPGA_SPARTAN2_OPS } 913bff4ffaSMatthias Fuchs 929dd611b8Swdenk #define XILINX_XC2S50E_DESC(iface, fn_table, cookie) \ 93*4e9acc16SMichal Simek { xilinx_spartan2, iface, XILINX_XC2S50E_SIZE, fn_table, cookie, \ 94*4e9acc16SMichal Simek FPGA_SPARTAN2_OPS } 959dd611b8Swdenk 969dd611b8Swdenk #define XILINX_XC2S100E_DESC(iface, fn_table, cookie) \ 97*4e9acc16SMichal Simek { xilinx_spartan2, iface, XILINX_XC2S100E_SIZE, fn_table, cookie, \ 98*4e9acc16SMichal Simek FPGA_SPARTAN2_OPS } 999dd611b8Swdenk 1009dd611b8Swdenk #define XILINX_XC2S150E_DESC(iface, fn_table, cookie) \ 101*4e9acc16SMichal Simek { xilinx_spartan2, iface, XILINX_XC2S150E_SIZE, fn_table, cookie, \ 102*4e9acc16SMichal Simek FPGA_SPARTAN2_OPS } 1039dd611b8Swdenk 1049dd611b8Swdenk #define XILINX_XC2S200E_DESC(iface, fn_table, cookie) \ 105*4e9acc16SMichal Simek { xilinx_spartan2, iface, XILINX_XC2S200E_SIZE, fn_table, cookie, \ 106*4e9acc16SMichal Simek FPGA_SPARTAN2_OPS } 1079dd611b8Swdenk 1089dd611b8Swdenk #define XILINX_XC2S300E_DESC(iface, fn_table, cookie) \ 109*4e9acc16SMichal Simek { xilinx_spartan2, iface, XILINX_XC2S300E_SIZE, fn_table, cookie, \ 110*4e9acc16SMichal Simek FPGA_SPARTAN2_OPS } 1119dd611b8Swdenk 112c609719bSwdenk #endif /* _SPARTAN2_H_ */ 113