Searched hist:"0 d6faf2bd0d12642e8b2c428d62c285f4ee28b9d" (Results 1 – 3 of 3) sorted by relevance
| /rk3399_rockchip-uboot/arch/arm/include/asm/arch-fsl-layerscape/ |
| H A D | immap_lsch2.h | 0d6faf2bd0d12642e8b2c428d62c285f4ee28b9d Mon Dec 07 08:58:54 UTC 2015 Mingkai Hu <Mingkai.hu@freescale.com> armv8/ls1043a: Implement workaround for PEX erratum A009929
Consecutive write transactions from core to PCI express outbound
path hangs after 25 to 30 transactions depending on core freq.
This erratum enable the mbist clock through COP register setting.
Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
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| H A D | config.h | 0d6faf2bd0d12642e8b2c428d62c285f4ee28b9d Mon Dec 07 08:58:54 UTC 2015 Mingkai Hu <Mingkai.hu@freescale.com> armv8/ls1043a: Implement workaround for PEX erratum A009929
Consecutive write transactions from core to PCI express outbound
path hangs after 25 to 30 transactions depending on core freq.
This erratum enable the mbist clock through COP register setting.
Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
|
| /rk3399_rockchip-uboot/arch/arm/cpu/armv8/fsl-layerscape/ |
| H A D | soc.c | 0d6faf2bd0d12642e8b2c428d62c285f4ee28b9d Mon Dec 07 08:58:54 UTC 2015 Mingkai Hu <Mingkai.hu@freescale.com> armv8/ls1043a: Implement workaround for PEX erratum A009929
Consecutive write transactions from core to PCI express outbound
path hangs after 25 to 30 transactions depending on core freq.
This erratum enable the mbist clock through COP register setting.
Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
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