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Searched +full:zynqmp +full:- +full:firmware (Results 1 – 25 of 45) sorted by relevance

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/OK3568_Linux_fs/kernel/Documentation/ABI/stable/
H A Dsysfs-driver-firmware-zynqmp1 What: /sys/devices/platform/firmware\:zynqmp-firmware/ggs*
11 The register is reset during system or power-on
17 # cat /sys/devices/platform/firmware\:zynqmp-firmware/ggs0
18 # echo <value> > /sys/devices/platform/firmware\:zynqmp-firmware/ggs0
22 # cat /sys/devices/platform/firmware\:zynqmp-firmware/ggs0
23 # echo 0x1234ABCD > /sys/devices/platform/firmware\:zynqmp-firmware/ggs0
27 What: /sys/devices/platform/firmware\:zynqmp-firmware/pggs*
38 This register is only reset by the power-on reset
46 # cat /sys/devices/platform/firmware\:zynqmp-firmware/pggs0
47 # echo <value> > /sys/devices/platform/firmware\:zynqmp-firmware/pggs0
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/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/power/reset/
H A Dxlnx,zynqmp-power.txt1 --------------------------------------------------------------------
3 --------------------------------------------------------------------
4 The zynqmp-power node describes the power management configurations.
8 - compatible: Must contain: "xlnx,zynqmp-power"
9 - interrupts: Interrupt specifier
12 - mbox-names : Name given to channels seen in the 'mboxes' property.
13 "tx" - Mailbox corresponding to transmit path
14 "rx" - Mailbox corresponding to receive path
15 - mboxes : Standard property to specify a Mailbox. Each value of
18 that will be the phandle to the intended sub-mailbox
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/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/firmware/xilinx/
H A Dxlnx,zynqmp-firmware.txt1 -----------------------------------------------------------------
2 Device Tree Bindings for the Xilinx Zynq MPSoC Firmware Interface
3 -----------------------------------------------------------------
5 The zynqmp-firmware node describes the interface to platform firmware.
6 ZynqMP has an interface to communicate with secure firmware. Firmware
7 driver provides an interface to firmware APIs. Interface APIs can be
14 - compatible: Must contain any of below:
15 "xlnx,zynqmp-firmware" for Zynq Ultrascale+ MPSoC
16 "xlnx,versal-firmware" for Versal
17 - method: The method of calling the PM-API firmware layer.
[all …]
/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/crypto/
H A Dxlnx,zynqmp-aes.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/crypto/xlnx,zynqmp-aes.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Xilinx ZynqMP AES-GCM Hardware Accelerator Device Tree Bindings
10 - Kalyani Akula <kalyani.akula@xilinx.com>
11 - Michal Simek <michal.simek@xilinx.com>
14 The ZynqMP AES-GCM hardened cryptographic accelerator is used to
19 const: xlnx,zynqmp-aes
22 - compatible
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/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/fpga/
H A Dxlnx,zynqmp-pcap-fpga.txt2 The ZynqMP SoC uses the PCAP (Processor configuration Port) to configure the
3 Programmable Logic (PL). The configuration uses the firmware interface.
6 - compatible: should contain "xlnx,zynqmp-pcap-fpga"
10 fpga-region0 {
11 compatible = "fpga-region";
12 fpga-mgr = <&zynqmp_pcap>;
13 #address-cells = <0x1>;
14 #size-cells = <0x1>;
17 firmware {
18 zynqmp_firmware: zynqmp-firmware {
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/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/clock/
H A Dxlnx,zynqmp-clk.txt1 --------------------------------------------------------------------------
3 Zynq MPSoC firmware interface
4 --------------------------------------------------------------------------
12 - #clock-cells: Must be 1
13 - compatible: Must contain: "xlnx,zynqmp-clk"
14 - clocks: List of clock specifiers which are external input
18 - clock-names: List of clock names which are exteral input clocks
22 Input clocks for zynqmp Ultrascale+ clock controller:
26 - pss_ref_clk (PS reference clock)
27 - video_clk (reference clock for video system )
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H A Dxlnx,versal-clk.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/xlnx,versal-clk.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Michal Simek <michal.simek@xilinx.com>
11 - Jolly Shah <jolly.shah@xilinx.com>
12 - Rajan Vaja <rajan.vaja@xilinx.com>
23 const: xlnx,versal-clk
25 "#clock-cells":
32 - description: reference clock
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/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/nvmem/
H A Dxlnx,zynqmp-nvmem.txt1 --------------------------------------------------------------------------
2 = Zynq UltraScale+ MPSoC nvmem firmware driver binding =
3 --------------------------------------------------------------------------
5 like soc revision, IDCODE... etc, By using the firmware interface.
8 - compatible: should be "xlnx,zynqmp-nvmem-fw"
14 -------
16 -------
17 firmware {
18 zynqmp_firmware: zynqmp-firmware {
19 compatible = "xlnx,zynqmp-firmware";
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/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/reset/
H A Dxlnx,zynqmp-reset.txt1 --------------------------------------------------------------------------
3 --------------------------------------------------------------------------
7 about zynqmp resets.
13 - compatible: "xlnx,zynqmp-reset" for Zynq UltraScale+ MPSoC platform
14 "xlnx,versal-reset" for Versal platform
15 - #reset-cells: Specifies the number of cells needed to encode reset
18 -------
20 -------
22 firmware {
23 zynqmp_firmware: zynqmp-firmware {
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/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/power/
H A Dxlnx,zynqmp-genpd.txt1 -----------------------------------------------------------
3 -----------------------------------------------------------
4 The binding for zynqmp-power-controller follow the common
7 [1] Documentation/devicetree/bindings/power/power-domain.yaml
12 - Below property should be in zynqmp-firmware node.
13 - #power-domain-cells: Number of cells in a PM domain specifier. Must be 1.
16 include/dt-bindings/power/xlnx-zynqmp-power.h.
18 -------
20 -------
22 firmware {
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/OK3568_Linux_fs/buildroot/board/zynqmp/patches/uboot/
H A D0002-arm64-zynqmp-Enable-booting-to-ATF.patch4 Subject: [PATCH] arm64: zynqmp: Enable booting to ATF
6 U-Boot is now able to boot to ARM Trusted Firmware (ATF). The boot
7 flow is SPL(EL3) loads ATF and full u-boot and jump to ATF(EL3) which
8 pass control to full u-boot(EL2). This has been tested on zcu106, so
12 '-O arm-trusted-firmware' to mkimage.
14 Signed-off-by: Luca Ceresoli <luca@lucaceresoli.net>
15 Signed-off-by: Michal Simek <michal.simek@xilinx.com>
16 Backported from upstream: http://git.denx.de/?p=u-boot.git;a=commit;h=5e3cac50cc981e01d9072241035a8…
17 ---
28 diff --git a/configs/xilinx_zynqmp_zc1751_xm015_dc1_defconfig b/configs/xilinx_zynqmp_zc1751_xm015_…
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/OK3568_Linux_fs/kernel/drivers/firmware/xilinx/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0
4 menu "Zynq MPSoC Firmware Drivers"
8 bool "Enable Xilinx Zynq MPSoC firmware interface"
13 Firmware interface driver is used by different
14 drivers to communicate with the firmware for
16 Say yes to enable ZynqMP firmware interface driver.
20 bool "Enable Xilinx Zynq MPSoC firmware debug APIs"
23 Say yes to enable ZynqMP firmware interface debug APIs.
H A Dzynqmp-debug.c1 // SPDX-License-Identifier: GPL-2.0
3 * Xilinx Zynq MPSoC Firmware layer for debugfs APIs
5 * Copyright (C) 2014-2018 Xilinx, Inc.
19 #include <linux/firmware/xlnx-zynqmp.h>
20 #include "zynqmp-debug.h"
41 * zynqmp_pm_argument_value() - Extract argument value from a PM-API request
42 * @arg: Entered PM-API argument in string format
61 * get_pm_api_id() - Extract API-ID from a PM-API request
62 * @pm_api_req: Entered PM-API argument in string format
63 * @pm_id: API-ID
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H A Dzynqmp.c1 // SPDX-License-Identifier: GPL-2.0
3 * Xilinx Zynq MPSoC Firmware layer
5 * Copyright (C) 2014-2021 Xilinx, Inc.
13 #include <linux/arm-smccc.h>
25 #include <linux/firmware/xlnx-zynqmp.h>
26 #include "zynqmp-debug.h"
35 * struct pm_api_feature_data - PM API Feature data
53 * zynqmp_pm_ret_code() - Convert PMU-FW error codes to Linux error codes
65 return -ENOTSUPP; in zynqmp_pm_ret_code()
67 return -EACCES; in zynqmp_pm_ret_code()
[all …]
/OK3568_Linux_fs/buildroot/configs/
H A Dzynqmp_zcu106_defconfig2 BR2_GLOBAL_PATCH_DIR="board/zynqmp/patches/"
4 BR2_ROOTFS_POST_IMAGE_SCRIPT="board/zynqmp/post-image.sh"
7 BR2_LINUX_KERNEL_CUSTOM_REPO_URL="git://github.com/Xilinx/linux-xlnx.git"
8 BR2_LINUX_KERNEL_CUSTOM_REPO_VERSION="xilinx-v2017.4"
11 BR2_LINUX_KERNEL_INTREE_DTS_NAME="xilinx/zynqmp-zcu106-revA"
17 …GET_ARM_TRUSTED_FIRMWARE_CUSTOM_REPO_URL="https://github.com/ARM-software/arm-trusted-firmware.git"
19 BR2_TARGET_ARM_TRUSTED_FIRMWARE_PLATFORM="zynqmp"
24 BR2_TARGET_UBOOT_CUSTOM_REPO_URL="git://github.com/xilinx/u-boot-xlnx.git"
31 …tps://github.com/lucaceresoli/zynqmp-pmufw-binaries/raw/53fdb7b6c92860ceb0ec5fd14deee302f4a84269/b…
/OK3568_Linux_fs/u-boot/arch/arm/cpu/armv8/zynqmp/
H A DKconfig28 default "zynqmp"
35 default "zynqmp"
51 Expect a table of register-value pairs, e.g. "0x12345678 0x4321"
54 string "PMU firmware"
58 Include external PMUFW (Platform Management Unit FirmWare) to
62 bool "Configure ZynqMP USB"
76 Include psu_init to full u-boot. SPL include psu_init by default.
/OK3568_Linux_fs/kernel/Documentation/driver-api/xilinx/
H A Deemi.rst5 Xilinx Zynq MPSoC Firmware Interface
6 -------------------------------------
7 The zynqmp-firmware node describes the interface to platform firmware.
8 ZynqMP has an interface to communicate with secure firmware. Firmware
9 driver provides an interface to firmware APIs. Interface APIs can be
13 ----------------------------------------------
23 ------
30 - IOCTL_SET_PLL_FRAC_MODE 8
31 - IOCTL_GET_PLL_FRAC_MODE 9
32 - IOCTL_SET_PLL_FRAC_DATA 10
[all …]
/OK3568_Linux_fs/kernel/arch/arm64/boot/dts/xilinx/
H A Dzynqmp.dtsi1 // SPDX-License-Identifier: GPL-2.0+
3 * dts file for Xilinx ZynqMP
5 * (C) Copyright 2014 - 2019, Xilinx, Inc.
15 #include <dt-bindings/power/xlnx-zynqmp-power.h>
16 #include <dt-bindings/reset/xlnx-zynqmp-resets.h>
19 compatible = "xlnx,zynqmp";
20 #address-cells = <2>;
21 #size-cells = <2>;
24 #address-cells = <1>;
25 #size-cells = <0>;
[all …]
/OK3568_Linux_fs/kernel/drivers/nvmem/
H A Dzynqmp_nvmem.c1 // SPDX-License-Identifier: GPL-2.0+
7 #include <linux/nvmem-provider.h>
10 #include <linux/firmware/xlnx-zynqmp.h>
30 dev_dbg(priv->dev, "Read chipid val %x %x\n", idcode, version); in zynqmp_nvmem_read()
37 .name = "zynqmp-nvmem",
45 { .compatible = "xlnx,zynqmp-nvmem-fw", },
52 struct device *dev = &pdev->dev; in zynqmp_nvmem_probe()
57 return -ENOMEM; in zynqmp_nvmem_probe()
59 priv->dev = dev; in zynqmp_nvmem_probe()
64 priv->nvmem = devm_nvmem_register(dev, &econfig); in zynqmp_nvmem_probe()
[all …]
/OK3568_Linux_fs/buildroot/boot/uboot/
H A DConfig.in2 bool "U-Boot"
4 Build "Das U-Boot" Boot Monitor
6 https://www.denx.de/wiki/U-Boot
17 Select this option if you use a recent U-Boot version (2015.04
23 Select this option if you use an old U-Boot (older than
30 string "U-Boot board name"
32 One of U-Boot supported boards to be built.
33 This will be suffixed with _config to meet U-Boot standard
34 naming. See boards.cfg in U-Boot source code for the list of
39 prompt "U-Boot Version"
[all …]
/OK3568_Linux_fs/kernel/drivers/clk/zynqmp/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0
4 bool "Support for Xilinx ZynqMP Ultrascale+ clock controllers"
8 Support for the Zynqmp Ultrascale clock controller.
9 It has a dependency on the PMU firmware.
/OK3568_Linux_fs/kernel/drivers/fpga/
H A Dzynqmp-fpga.c1 // SPDX-License-Identifier: GPL-2.0+
6 #include <linux/dma-mapping.h>
7 #include <linux/fpga/fpga-mgr.h>
13 #include <linux/firmware/xlnx-zynqmp.h>
19 * struct zynqmp_fpga_priv - Private data structure
34 priv = mgr->priv; in zynqmp_fpga_ops_write_init()
35 priv->flags = info->flags; in zynqmp_fpga_ops_write_init()
49 priv = mgr->priv; in zynqmp_fpga_ops_write()
51 kbuf = dma_alloc_coherent(priv->dev, size, &dma_addr, GFP_KERNEL); in zynqmp_fpga_ops_write()
53 return -ENOMEM; in zynqmp_fpga_ops_write()
[all …]
/OK3568_Linux_fs/kernel/drivers/soc/xilinx/
H A Dzynqmp_pm_domains.c1 // SPDX-License-Identifier: GPL-2.0
3 * ZynqMP Generic PM domain support
5 * Copyright (C) 2015-2019 Xilinx, Inc.
20 #include <linux/firmware/xlnx-zynqmp.h>
29 * struct zynqmp_pm_domain - Wrapper around struct generic_pm_domain
32 * @flags: ZynqMP PM domain flags
41 * zynqmp_gpd_is_active_wakeup_path() - Check if device is in wakeup source
64 * zynqmp_gpd_power_on() - Power on PM domain
78 ret = zynqmp_pm_set_requirement(pd->node_id, in zynqmp_gpd_power_on()
84 __func__, domain->name, pd->node_id, ret); in zynqmp_gpd_power_on()
[all …]
/OK3568_Linux_fs/kernel/drivers/reset/
H A Dreset-zynqmp.c1 // SPDX-License-Identifier: GPL-2.0+
10 #include <linux/reset-controller.h>
11 #include <linux/firmware/xlnx-zynqmp.h>
14 #define ZYNQMP_NR_RESETS (ZYNQMP_PM_RESET_END - ZYNQMP_PM_RESET_START)
39 return zynqmp_pm_reset_assert(priv->data->reset_id + id, in zynqmp_reset_assert()
48 return zynqmp_pm_reset_assert(priv->data->reset_id + id, in zynqmp_reset_deassert()
59 err = zynqmp_pm_reset_get_status(priv->data->reset_id + id, &val); in zynqmp_reset_status()
71 return zynqmp_pm_reset_assert(priv->data->reset_id + id, in zynqmp_reset_reset()
78 return reset_spec->args[0]; in zynqmp_reset_of_xlate()
102 priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL); in zynqmp_reset_probe()
[all …]
/OK3568_Linux_fs/kernel/drivers/crypto/xilinx/
H A Dzynqmp-aes-gcm.c1 // SPDX-License-Identifier: GPL-2.0
3 * Xilinx ZynqMP AES Driver.
13 #include <linux/dma-mapping.h>
18 #include <linux/firmware/xlnx-zynqmp.h>
82 struct device *dev = tfm_ctx->dev; in zynqmp_aes_aead_cipher()
92 if (tfm_ctx->keysrc == ZYNQMP_AES_KUP_KEY) in zynqmp_aes_aead_cipher()
93 dma_size = req->cryptlen + ZYNQMP_AES_KEY_SIZE in zynqmp_aes_aead_cipher()
96 dma_size = req->cryptlen + GCM_AES_IV_SIZE; in zynqmp_aes_aead_cipher()
100 return -ENOMEM; in zynqmp_aes_aead_cipher()
106 return -ENOMEM; in zynqmp_aes_aead_cipher()
[all …]

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