1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0+
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * Copyright (C) 2019 Xilinx, Inc.
4*4882a593Smuzhiyun */
5*4882a593Smuzhiyun
6*4882a593Smuzhiyun #include <linux/module.h>
7*4882a593Smuzhiyun #include <linux/nvmem-provider.h>
8*4882a593Smuzhiyun #include <linux/of.h>
9*4882a593Smuzhiyun #include <linux/platform_device.h>
10*4882a593Smuzhiyun #include <linux/firmware/xlnx-zynqmp.h>
11*4882a593Smuzhiyun
12*4882a593Smuzhiyun #define SILICON_REVISION_MASK 0xF
13*4882a593Smuzhiyun
14*4882a593Smuzhiyun struct zynqmp_nvmem_data {
15*4882a593Smuzhiyun struct device *dev;
16*4882a593Smuzhiyun struct nvmem_device *nvmem;
17*4882a593Smuzhiyun };
18*4882a593Smuzhiyun
zynqmp_nvmem_read(void * context,unsigned int offset,void * val,size_t bytes)19*4882a593Smuzhiyun static int zynqmp_nvmem_read(void *context, unsigned int offset,
20*4882a593Smuzhiyun void *val, size_t bytes)
21*4882a593Smuzhiyun {
22*4882a593Smuzhiyun int ret;
23*4882a593Smuzhiyun int idcode, version;
24*4882a593Smuzhiyun struct zynqmp_nvmem_data *priv = context;
25*4882a593Smuzhiyun
26*4882a593Smuzhiyun ret = zynqmp_pm_get_chipid(&idcode, &version);
27*4882a593Smuzhiyun if (ret < 0)
28*4882a593Smuzhiyun return ret;
29*4882a593Smuzhiyun
30*4882a593Smuzhiyun dev_dbg(priv->dev, "Read chipid val %x %x\n", idcode, version);
31*4882a593Smuzhiyun *(int *)val = version & SILICON_REVISION_MASK;
32*4882a593Smuzhiyun
33*4882a593Smuzhiyun return 0;
34*4882a593Smuzhiyun }
35*4882a593Smuzhiyun
36*4882a593Smuzhiyun static struct nvmem_config econfig = {
37*4882a593Smuzhiyun .name = "zynqmp-nvmem",
38*4882a593Smuzhiyun .owner = THIS_MODULE,
39*4882a593Smuzhiyun .word_size = 1,
40*4882a593Smuzhiyun .size = 1,
41*4882a593Smuzhiyun .read_only = true,
42*4882a593Smuzhiyun };
43*4882a593Smuzhiyun
44*4882a593Smuzhiyun static const struct of_device_id zynqmp_nvmem_match[] = {
45*4882a593Smuzhiyun { .compatible = "xlnx,zynqmp-nvmem-fw", },
46*4882a593Smuzhiyun { /* sentinel */ },
47*4882a593Smuzhiyun };
48*4882a593Smuzhiyun MODULE_DEVICE_TABLE(of, zynqmp_nvmem_match);
49*4882a593Smuzhiyun
zynqmp_nvmem_probe(struct platform_device * pdev)50*4882a593Smuzhiyun static int zynqmp_nvmem_probe(struct platform_device *pdev)
51*4882a593Smuzhiyun {
52*4882a593Smuzhiyun struct device *dev = &pdev->dev;
53*4882a593Smuzhiyun struct zynqmp_nvmem_data *priv;
54*4882a593Smuzhiyun
55*4882a593Smuzhiyun priv = devm_kzalloc(dev, sizeof(struct zynqmp_nvmem_data), GFP_KERNEL);
56*4882a593Smuzhiyun if (!priv)
57*4882a593Smuzhiyun return -ENOMEM;
58*4882a593Smuzhiyun
59*4882a593Smuzhiyun priv->dev = dev;
60*4882a593Smuzhiyun econfig.dev = dev;
61*4882a593Smuzhiyun econfig.reg_read = zynqmp_nvmem_read;
62*4882a593Smuzhiyun econfig.priv = priv;
63*4882a593Smuzhiyun
64*4882a593Smuzhiyun priv->nvmem = devm_nvmem_register(dev, &econfig);
65*4882a593Smuzhiyun
66*4882a593Smuzhiyun return PTR_ERR_OR_ZERO(priv->nvmem);
67*4882a593Smuzhiyun }
68*4882a593Smuzhiyun
69*4882a593Smuzhiyun static struct platform_driver zynqmp_nvmem_driver = {
70*4882a593Smuzhiyun .probe = zynqmp_nvmem_probe,
71*4882a593Smuzhiyun .driver = {
72*4882a593Smuzhiyun .name = "zynqmp-nvmem",
73*4882a593Smuzhiyun .of_match_table = zynqmp_nvmem_match,
74*4882a593Smuzhiyun },
75*4882a593Smuzhiyun };
76*4882a593Smuzhiyun
77*4882a593Smuzhiyun module_platform_driver(zynqmp_nvmem_driver);
78*4882a593Smuzhiyun
79*4882a593Smuzhiyun MODULE_AUTHOR("Michal Simek <michal.simek@xilinx.com>, Nava kishore Manne <navam@xilinx.com>");
80*4882a593Smuzhiyun MODULE_DESCRIPTION("ZynqMP NVMEM driver");
81*4882a593Smuzhiyun MODULE_LICENSE("GPL");
82