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Searched +full:tmod +full:- +full:calibration (Results 1 – 11 of 11) sorted by relevance

/OK3568_Linux_fs/kernel/drivers/thermal/
H A Duniphier_thermal.c1 // SPDX-License-Identifier: GPL-2.0
3 * uniphier_thermal.c - Socionext UniPhier thermal driver
5 * Copyright 2016-2017 Socionext Inc.
60 #define TMOD 0x0928 macro
93 struct regmap *map = tdev->regmap; in uniphier_tm_initialize_sensor()
99 regmap_write_bits(map, tdev->data->block_base + PVTCTLEN, in uniphier_tm_initialize_sensor()
104 * TMODCOEF shows non-zero and PVT refers the value internally. in uniphier_tm_initialize_sensor()
109 ret = regmap_read(map, tdev->data->map_base + TMODCOEF, &val); in uniphier_tm_initialize_sensor()
114 ret = of_property_read_u32_array(tdev->dev->of_node, in uniphier_tm_initialize_sensor()
115 "socionext,tmod-calibration", in uniphier_tm_initialize_sensor()
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/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/thermal/
H A Dsocionext,uniphier-thermal.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/thermal/socionext,uniphier-thermal.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
15 - Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
20 - socionext,uniphier-pxs2-thermal
21 - socionext,uniphier-ld20-thermal
22 - socionext,uniphier-pxs3-thermal
27 "#thermal-sensor-cells":
30 socionext,tmod-calibration:
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/OK3568_Linux_fs/u-boot/arch/arm/mach-sunxi/
H A Ddram_sun8i_a33.c4 * (C) Copyright 2007-2015 Allwinner Technology Co.
9 * SPDX-License-Identifier: GPL-2.0+
18 /* PLL runs at 2x dram-clk, controller runs at PLL / 4 (dram-clk / 2) */
38 writel(MCTL_CR_CS1_CONTROL(para->cs1) | MCTL_CR_UNKNOWN | in mctl_set_cr()
40 (para->seq ? MCTL_CR_SEQUENCE : 0) | in mctl_set_cr()
41 ((para->bus_width == 16) ? MCTL_CR_BUSW16 : MCTL_CR_BUSW8) | in mctl_set_cr()
42 MCTL_CR_PAGE_SIZE(para->page_size) | MCTL_CR_ROW(para->rows) | in mctl_set_cr()
43 MCTL_CR_BANK(para->bank) | MCTL_CR_RANK(para->rank), in mctl_set_cr()
44 &mctl_com->cr); in mctl_set_cr()
49 u8 orig_rank = para->rank; in auto_detect_dram_size()
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H A Ddram_sun9i.c4 * (C) Copyright 2007-2015
9 * Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
11 * SPDX-License-Identifier: GPL-2.0+
29 * Allwinner as part of the open-source bootloader release (refer to
30 * https://github.com/allwinner-zh/bootloader.git) and augments the upstream
39 * Note that the Zynq-documentation provides a very close match for the DDR
45 * (i.e. the rules for MEMC_FREQ_RATIO=2 from the Zynq-documentation apply).
51 * 1) Only DDR3 support is implemented, as our test platform (the A80-Q7
53 * 2) Only 2T-mode has been implemented and tested.
65 * The driver should be driven from a device-tree based configuration that
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H A Ddram_sun8i_a83t.c4 * (C) Copyright 2007-2015 Allwinner Technology Co.
9 * SPDX-License-Identifier: GPL-2.0+
37 writel(MCTL_CR_CS1_CONTROL(para->cs1) | MCTL_CR_UNKNOWN | in mctl_set_cr()
38 MCTL_CR_CHANNEL(1) | MCTL_CR_DRAM_TYPE(para->dram_type) | in mctl_set_cr()
39 (para->seq ? MCTL_CR_SEQUENCE : 0) | in mctl_set_cr()
40 ((para->bus_width == 16) ? MCTL_CR_BUSW16 : MCTL_CR_BUSW8) | in mctl_set_cr()
41 MCTL_CR_PAGE_SIZE(para->page_size) | MCTL_CR_ROW(para->rows) | in mctl_set_cr()
42 MCTL_CR_BANK(para->bank) | MCTL_CR_RANK(para->rank), in mctl_set_cr()
43 &mctl_com->cr); in mctl_set_cr()
48 u8 orig_rank = para->rank; in auto_detect_dram_size()
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/OK3568_Linux_fs/u-boot/drivers/ddr/fsl/
H A Dctrl_regs.c2 * Copyright 2008-2014 Freescale Semiconductor, Inc.
4 * SPDX-License-Identifier: GPL-2.0+
29 * Rtt(nominal) - DDR2:
34 * Rtt(nominal) - DDR3:
49 * if (popts->dimmslot[i].num_valid_cs
50 * && (popts->cs_local_opts[2*i].odt_rd_cfg
51 * || popts->cs_local_opts[2*i].odt_wr_cfg)) {
155 unsigned int ap_n_en = 0; /* Chip select n auto-precharge enable */ in set_csn_config()
174 if (!popts->memctl_interleaving) in set_csn_config()
176 switch (popts->memctl_interleaving_mode) { in set_csn_config()
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/OK3568_Linux_fs/u-boot/drivers/ddr/altera/
H A Dsequencer.c2 * Copyright Altera Corporation (C) 2012-2015
4 * SPDX-License-Identifier: BSD-3-Clause
41 * In order to reduce ROM size, most of the selectable calibration steps are
42 * decided at compile time based on the user's calibration mode selection,
45 * However, to support simulation-time selection of fast simulation mode, where
48 * check, which is based on the rtl-supplied value, or we dynamically compute
49 * the value to use based on the dynamically-chosen calibration mode
59 /* calibration steps requested by the rtl */
65 * non-skip and skip values
67 * The mask is set to include all bits when not-skipping, but is
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/OK3568_Linux_fs/kernel/arch/arm/boot/dts/
H A Duniphier-pxs2.dtsi1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
5 // Copyright (C) 2015-2016 Socionext Inc.
8 #include <dt-bindings/gpio/uniphier-gpio.h>
9 #include <dt-bindings/thermal/thermal.h>
12 compatible = "socionext,uniphier-pxs2";
13 #address-cells = <1>;
14 #size-cells = <1>;
17 #address-cells = <1>;
18 #size-cells = <0>;
22 compatible = "arm,cortex-a9";
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/OK3568_Linux_fs/kernel/arch/arm64/boot/dts/socionext/
H A Duniphier-pxs3.dtsi1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/gpio/uniphier-gpio.h>
10 #include <dt-bindings/thermal/thermal.h>
13 compatible = "socionext,uniphier-pxs3";
14 #address-cells = <2>;
15 #size-cells = <2>;
16 interrupt-parent = <&gic>;
19 #address-cells = <2>;
20 #size-cells = <0>;
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H A Duniphier-ld20.dtsi1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
5 // Copyright (C) 2015-2016 Socionext Inc.
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/gpio/uniphier-gpio.h>
10 #include <dt-bindings/thermal/thermal.h>
13 compatible = "socionext,uniphier-ld20";
14 #address-cells = <2>;
15 #size-cells = <2>;
16 interrupt-parent = <&gic>;
19 #address-cells = <2>;
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/OK3568_Linux_fs/u-boot/drivers/ram/rockchip/
H A Ddmc-rk3368.c4 * SPDX-License-Identifier: GPL-2.0
10 #include <dt-bindings/memory/rk3368-dmc.h>
11 #include <dt-structs.h>
126 ((n <= 8) ? ((n - 4) << 9) : (((n >> 1) & 0x7) << 9))
128 ((((n - 4) & 0x7) << 4) | (((n - 4) & 0x8) >> 2))
136 (((n - 5) & 0x7) << 3)
144 rk_setreg(&grf->ddrc0_con0, NOC_RSP_ERR_STALL); in ddr_set_noc_spr_err_stall()
146 rk_clrreg(&grf->ddrc0_con0, NOC_RSP_ERR_STALL); in ddr_set_noc_spr_err_stall()
152 rk_setreg(&grf->ddrc0_con0, MSCH0_MAINDDR3_DDR3); in ddr_set_ddr3_mode()
154 rk_clrreg(&grf->ddrc0_con0, MSCH0_MAINDDR3_DDR3); in ddr_set_ddr3_mode()
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