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/OK3568_Linux_fs/kernel/sound/soc/codecs/
H A Dtda7419.c1 // SPDX-License-Identifier: GPL-2.0-only
136 if (tvc->reg == tvc->rreg) in tda7419_vol_is_stereo()
146 (struct tda7419_vol_control *)kcontrol->private_value; in tda7419_vol_info()
148 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER; in tda7419_vol_info()
149 uinfo->count = tda7419_vol_is_stereo(tvc) ? 2 : 1; in tda7419_vol_info()
150 uinfo->value.integer.min = tvc->min; in tda7419_vol_info()
151 uinfo->value.integer.max = tvc->max; in tda7419_vol_info()
163 val = 0 - val; in tda7419_vol_get_value()
166 val = val - thresh; in tda7419_vol_get_value()
168 val = thresh - val; in tda7419_vol_get_value()
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/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/opp/
H A Dopp.txt2 ----------------------------------------------------
4 Devices work at voltage-current-frequency combinations and some implementations
13 Binding 1: operating-points
16 This binding only supports voltage-frequency pairs.
19 - operating-points: An array of 2-tuples items, and each item consists
20 of frequency and voltage like <freq-kHz vol-uV>.
21 freq: clock frequency in kHz
27 compatible = "arm,cortex-a9";
29 next-level-cache = <&L2>;
30 operating-points = <
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/OK3568_Linux_fs/kernel/init/
H A Dcalibrate.c1 // SPDX-License-Identifier: GPL-2.0
29 * Also, this code tries to handle non-maskable asynchronous events
32 #define DELAY_CALIBRATION_TICKS ((HZ < 100) ? 1 : (HZ/100))
44 int max = -1; /* index of measured_times with max/min values or not set */ in calibrate_delay_direct()
45 int min = -1; in calibrate_delay_direct()
55 * will not do. As we don't really know whether jiffy switch in calibrate_delay_direct()
60 * 1. pre_start <- When we are sure that jiffy switch hasn't happened in calibrate_delay_direct()
61 * 2. check jiffy switch in calibrate_delay_direct()
62 * 3. start <- timer value before or after jiffy switch in calibrate_delay_direct()
63 * 4. post_start <- When we are sure that jiffy switch has happened in calibrate_delay_direct()
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/OK3568_Linux_fs/kernel/drivers/iio/pressure/
H A Dzpa2326.c1 // SPDX-License-Identifier: GPL-2.0-only
34 * - get device out of low power mode,
35 * - setup hardware sampling period,
36 * - at end of period, upon data ready interrupt: pop pressure samples out of
38 * - when no longer needed, stop sampling process by putting device into
44 * Note that hardware sampling frequency is taken into account only when
70 /* 200 ms should be enough for the longest conversion time in one-shot mode. */
71 #define ZPA2326_CONVERSION_JIFFIES (HZ / 5)
78 * struct zpa2326_frequency - Hardware sampling frequency descriptor
79 * @hz : Frequency in Hertz.
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/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/mfd/
H A Dqcom-rpm.txt8 - compatible:
12 "qcom,rpm-apq8064"
13 "qcom,rpm-msm8660"
14 "qcom,rpm-msm8960"
15 "qcom,rpm-ipq8064"
16 "qcom,rpm-mdm9615"
18 - reg:
20 Value type: <prop-encoded-array>
23 - interrupts:
25 Value type: <prop-encoded-array>
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/OK3568_Linux_fs/u-boot/drivers/clk/rockchip/
H A Dclk_rk3399.c5 * SPDX-License-Identifier: GPL-2.0
9 #include <clk-uclass.h>
11 #include <dt-structs.h>
21 #include <dt-bindings/clock/rk3399-cru.h>
45 ((input_rate) / (output_rate) - 1);
48 #define PLL_DIVISORS(hz, _refdiv, _postdiv1, _postdiv2) {\ argument
50 .fbdiv = (u32)((u64)hz * _refdiv * _postdiv1 * _postdiv2 / OSC_HZ),\
51 .postdiv1 = _postdiv1, .postdiv2 = _postdiv2, .freq = hz};
261 CLK_SPI_PLL_SEL_MASK = ((1 < CLK_SPI_PLL_SEL_WIDTH) - 1),
265 CLK_SPI_PLL_DIV_CON_MASK = ((1 << CLK_SPI_PLL_DIV_CON_WIDTH) - 1),
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H A Dclk_px30.c4 * SPDX-License-Identifier: GPL-2.0
9 #include <clk-uclass.h>
19 #include <dt-bindings/clock/px30-cru.h>
120 printf("%s: the frequency can't be 0 Hz\n", __func__); in pll_clk_set_by_auto()
139 rate->postdiv1 = postdiv1; in pll_clk_set_by_auto()
140 rate->postdiv2 = postdiv2; in pll_clk_set_by_auto()
149 diff_khz = vco_khz - fbdiv * fref_khz; in pll_clk_set_by_auto()
152 diff_khz = fref_khz - diff_khz; in pll_clk_set_by_auto()
159 rate->refdiv = refdiv; in pll_clk_set_by_auto()
160 rate->fbdiv = fbdiv; in pll_clk_set_by_auto()
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H A Dclk_rk3066.c5 * SPDX-License-Identifier: GPL-2.0
9 #include <clk-uclass.h>
11 #include <dt-structs.h>
20 #include <dt-bindings/clock/rk3066a-cru.h>
21 #include <dm/device-internal.h>
23 #include <dm/uclass-internal.h>
91 ((input_rate) / (output_rate) - 1);
95 #define PLL_DIVISORS(hz, _nr, _no) {\ argument
96 .nr = _nr, .nf = (u32)((u64)hz * _nr * _no / OSC_HZ), .no = _no};\
97 _Static_assert(((u64)hz * _nr * _no / OSC_HZ) * OSC_HZ /\
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H A Dclk_rk3188.c5 * SPDX-License-Identifier: GPL-2.0
9 #include <clk-uclass.h>
11 #include <dt-structs.h>
21 #include <dt-bindings/clock/rk3188-cru.h>
22 #include <dm/device-internal.h>
24 #include <dm/uclass-internal.h>
93 #define PLL_DIVISORS(hz, _nr, _no) {\ argument
94 .nr = _nr, .nf = (u32)((u64)hz * _nr * _no / OSC_HZ), .no = _no};\
95 _Static_assert(((u64)hz * _nr * _no / OSC_HZ) * OSC_HZ /\
96 (_nr * _no) == hz, #hz "Hz cannot be hit with PLL "\
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H A Dclk_rk3288.c4 * SPDX-License-Identifier: GPL-2.0
9 #include <clk-uclass.h>
11 #include <dt-structs.h>
20 #include <dt-bindings/clock/rk3288-cru.h>
21 #include <dm/device-internal.h>
23 #include <dm/uclass-internal.h>
212 #define PLL_DIVISORS(hz, _nr, _no) {\ argument
213 .nr = _nr, .nf = (u32)((u64)hz * _nr * _no / OSC_HZ), .no = _no};\
214 _Static_assert(((u64)hz * _nr * _no / OSC_HZ) * OSC_HZ /\
215 (_nr * _no) == hz, #hz "Hz cannot be hit with PLL "\
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H A Dclk_rk3368.c3 * Author: Andy Yan <andy.yan@rock-chips.com>
5 * SPDX-License-Identifier: GPL-2.0
9 #include <clk-uclass.h>
11 #include <dt-structs.h>
21 #include <dt-bindings/clock/rk3368-cru.h>
106 #define PLL_DIVISORS(hz, _nr, _no) { \ argument
107 .nr = _nr, .nf = (u32)((u64)hz * _nr * _no / OSC_HZ), .no = _no}; \
108 _Static_assert(((u64)hz * _nr * _no / OSC_HZ) * OSC_HZ /\
109 (_nr * _no) == hz, #hz "Hz cannot be hit with PLL " \
153 printf("%s: the frequency can not be 0 Hz\n", __func__); in pll_para_config()
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/OK3568_Linux_fs/u-boot/arch/arm/mach-sunxi/
H A Dclock_sun4i.c4 * (C) Copyright 2007-2012
10 * SPDX-License-Identifier: GPL-2.0+
30 &ccm->cpu_ahb_apb0_cfg); in clock_init_safe()
31 writel(PLL1_CFG_DEFAULT, &ccm->pll1_cfg); in clock_init_safe()
37 &ccm->cpu_ahb_apb0_cfg); in clock_init_safe()
39 setbits_le32(&ccm->ahb_gate0, 0x1 << AHB_GATE_OFFSET_DMA); in clock_init_safe()
41 writel(PLL6_CFG_DEFAULT, &ccm->pll6_cfg); in clock_init_safe()
43 setbits_le32(&ccm->ahb_gate0, 0x1 << AHB_GATE_OFFSET_SATA); in clock_init_safe()
44 setbits_le32(&ccm->pll6_cfg, 0x1 << CCM_PLL6_CTRL_SATA_EN_SHIFT); in clock_init_safe()
58 &ccm->apb1_clk_div_cfg); in clock_init_uart()
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/OK3568_Linux_fs/kernel/drivers/clk/analogbits/
H A Dwrpll-cln28hpc.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2018-2019 SiFive, Inc.
16 * pre-determined set of performance points.
19 * - Analog Bits "Wide Range PLL Datasheet", version 2015.10.01
20 * - SiFive FU540-C000 Manual v1p0, Chapter 7 "Clocking and Reset"
21 * https://static.dev.sifive.com/FU540-C000-v1.0.pdf
28 #include <linux/clk/analogbits-wrpll-cln28hpc.h>
30 /* MIN_INPUT_FREQ: minimum input clock frequency, in Hz (Fref_min) */
33 /* MAX_INPUT_FREQ: maximum input clock frequency, in Hz (Fref_max) */
36 /* MIN_POST_DIVIDE_REF_FREQ: minimum post-divider reference frequency, in Hz */
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/OK3568_Linux_fs/u-boot/drivers/sound/
H A Dwm8994.c5 * SPDX-License-Identifier: GPL-2.0+
30 int in; /* Input frequency in Hz */
31 int out; /* output frequency in Hz */
38 int sysclk[WM8994_MAX_AIF]; /* System clock frequency in Hz */
39 int mclk[WM8994_MAX_AIF]; /* master clock frequency in Hz */
40 int aifclk[WM8994_MAX_AIF]; /* audio interface clock in Hz */
103 * @return int value 0 for success, -1 in case of error.
114 return -1; in wm8994_i2c_read()
141 return -1; in wm8994_update_bits()
158 * @return -1 for error and 0 Success.
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/OK3568_Linux_fs/kernel/include/linux/soundwire/
H A Dsdw.h1 /* SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) */
2 /* Copyright(c) 2015-17 Intel Corporation. */
71 * enum sdw_slave_status - Slave status
89 * @SDW_CLK_PRE_DEPREPARE: pre clock stop de-prepare
90 * @SDW_CLK_POST_DEPREPARE: post clock stop de-prepare
100 * enum sdw_command_response - Command response as defined by SDW spec
180 * enum sdw_p15_behave - Slave Port 15 behaviour when the Master attempts a
191 * enum sdw_dpn_type - Data port types
206 * enum sdw_clk_stop_mode - Clock Stop modes
209 * @SDW_CLK_STOP_MODE1: Slave may have entered a deeper power-saving mode,
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/OK3568_Linux_fs/kernel/drivers/iio/accel/
H A Dbma400_core.c1 // SPDX-License-Identifier: GPL-2.0-only
8 * - Support for power management
9 * - Support events and interrupts
10 * - Create channel for step count
11 * - Create channel for sensor time
27 * The G-range selection may be one of 2g, 4g, 8, or 16g. The scale may
50 int hz; member
68 switch (reg) { in bma400_is_writable_reg()
101 switch (reg) { in bma400_is_volatile_reg()
147 return &data->orientation; in bma400_accel_get_mount_matrix()
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/OK3568_Linux_fs/kernel/drivers/clk/hisilicon/
H A Dclk-hi6220-stub.c1 // SPDX-License-Identifier: GPL-2.0-only
11 #include <linux/clk-provider.h>
33 /* CPU dynamic frequency scaling */
71 regmap_read(stub_clk->dfs_map, ACPU_DFS_CUR_FREQ, &freq); in hi6220_acpu_get_freq()
80 /* set the frequency in sram */ in hi6220_acpu_set_freq()
81 regmap_write(stub_clk->dfs_map, ACPU_DFS_FREQ_REQ, freq); in hi6220_acpu_set_freq()
89 mbox_send_message(stub_clk->mbox, &data); in hi6220_acpu_set_freq()
99 /* check the constrained frequency */ in hi6220_acpu_round_freq()
100 regmap_read(stub_clk->dfs_map, ACPU_DFS_FLAG, &limit_flag); in hi6220_acpu_round_freq()
102 regmap_read(stub_clk->dfs_map, ACPU_DFS_FREQ_LMT, &limit_freq); in hi6220_acpu_round_freq()
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/OK3568_Linux_fs/kernel/include/linux/
H A Dtimex.h28 * Added defines for hybrid phase/frequency-lock loop.
32 * defines for PPS phase-lock loop.
46 * 1995-08-13 Torsten Duwe
47 * kernel PLL updated to 1994-12-13 specs (rfc-1589)
48 * 1997-08-30 Ulrich Windl
50 * 2004-08-12 Christoph Lameter
58 #define ADJ_ADJTIME 0x8000 /* switch between adjtime/adjtimex modes */
59 #define ADJ_OFFSET_SINGLESHOT 0x0001 /* old-fashioned adjtime */
60 #define ADJ_OFFSET_READONLY 0x2000 /* read-only adjtime */
73 * when an interrupt takes places versus a high speed, fine-grained
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/OK3568_Linux_fs/kernel/Documentation/admin-guide/media/
H A Dvivid.rst1 .. SPDX-License-Identifier: GPL-2.0
13 Each input can be a webcam, TV capture device, S-Video capture device or an HDMI
14 capture device. Each output can be an S-Video output device or an HDMI output
23 - Support for read()/write(), MMAP, USERPTR and DMABUF streaming I/O.
24 - A large list of test patterns and variations thereof
25 - Working brightness, contrast, saturation and hue controls
26 - Support for the alpha color component
27 - Full colorspace support, including limited/full RGB range
28 - All possible control types are present
29 - Support for various pixel aspect ratios and video aspect ratios
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/OK3568_Linux_fs/u-boot/arch/powerpc/cpu/mpc86xx/
H A Dspeed.c6 * (C) Copyright 2000-2002
9 * SPDX-License-Identifier: GPL-2.0+
25 volatile ccsr_gur_t *gur = &immap->im_gur; in get_sys_info()
28 plat_ratio = (gur->porpllsr) & 0x0000003e; in get_sys_info()
31 switch (plat_ratio) { in get_sys_info()
33 sys_info->freq_systembus = 16 * CONFIG_SYS_CLK_FREQ; in get_sys_info()
45 sys_info->freq_systembus = plat_ratio * CONFIG_SYS_CLK_FREQ; in get_sys_info()
48 sys_info->freq_systembus = 0; in get_sys_info()
52 e600_ratio = (gur->porpllsr) & 0x003f0000; in get_sys_info()
55 switch (e600_ratio) { in get_sys_info()
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/OK3568_Linux_fs/kernel/include/media/
H A Dtuner-types.h1 /* SPDX-License-Identifier: GPL-2.0 */
10 * enum param_type - type of the tuner pameters
27 * struct tuner_range - define the frequencies supported by the tuner
29 * @limit: Max frequency supported by that range, in 62.5 kHz
30 * (TV) or 62.5 Hz (Radio), as defined by
32 * @config: Value of the band switch byte (BB) to setup this mode.
43 * #) band switch byte (BB)
54 * struct tuner_params - Parameters to be used to setup the tuner. Those
55 * are used by drivers/media/tuners/tuner-types.c in
57 * the parameters are for tuners based on tda9887 IF-PLL
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/OK3568_Linux_fs/kernel/sound/drivers/vx/
H A Dvx_uer.c1 // SPDX-License-Identifier: GPL-2.0-or-later
17 * vx_modify_board_clock - tell the board that its clock has been modified
32 * vx_modify_board_inputs - resync audio inputs
44 * vx_read_one_cbit - read one bit from UER config
52 mutex_lock(&chip->lock); in vx_read_one_cbit()
53 if (chip->type >= VX_TYPE_VXPOCKET) { in vx_read_one_cbit()
62 mutex_unlock(&chip->lock); in vx_read_one_cbit()
67 * vx_write_one_cbit - write one bit to UER config
74 mutex_lock(&chip->lock); in vx_write_one_cbit()
82 mutex_unlock(&chip->lock); in vx_write_one_cbit()
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/OK3568_Linux_fs/kernel/sound/pci/hda/
H A Dhda_beep.c1 // SPDX-License-Identifier: GPL-2.0+
3 * Digital Beep Input Interface for HD-audio codec
18 DIGBEEP_HZ_STEP = 46875, /* 46.875 Hz */
19 DIGBEEP_HZ_MIN = 93750, /* 93.750 Hz */
26 struct hda_codec *codec = beep->codec; in generate_tone()
28 if (tone && !beep->playing) { in generate_tone()
30 if (beep->power_hook) in generate_tone()
31 beep->power_hook(beep, true); in generate_tone()
32 beep->playing = 1; in generate_tone()
34 snd_hda_codec_write(codec, beep->nid, 0, in generate_tone()
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/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/regulator/
H A Dmps,mp886x.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Jisheng Zhang <jszhang@kernel.org>
13 - $ref: regulator.yaml#
18 - mps,mp8867
19 - mps,mp8869
24 enable-gpios:
28 mps,fb-voltage-divider:
31 $ref: "/schemas/types.yaml#/definitions/uint32-array"
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/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/i2c/
H A Dnuvoton,npcm7xx-i2c.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/i2c/nuvoton,npcm7xx-i2c.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 both master and slave mode. Each controller can switch between master and slave
16 - Tali Perry <tali.perry1@gmail.com>
20 const: nuvoton,npcm7xx-i2c
32 clock-frequency:
33 description: Desired I2C bus clock frequency in Hz. If not specified,
34 the default 100 kHz frequency will be used.
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