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/OK3568_Linux_fs/kernel/arch/arm/mach-s3c/
H A Dcpufreq-utils-s3c24xx.c23 * s3c2410_cpufreq_setrefresh - set SDRAM refresh value
26 * Set the SDRAM refresh value appropriately for the configured
32 unsigned long refresh; in s3c2410_cpufreq_setrefresh() local
35 /* Reduce both the refresh time (in ns) and the frequency (in MHz) in s3c2410_cpufreq_setrefresh()
38 * This should work for HCLK up to 133MHz and refresh period up in s3c2410_cpufreq_setrefresh()
42 refresh = (cfg->freq.hclk / 100) * (board->refresh / 10); in s3c2410_cpufreq_setrefresh()
43 refresh = DIV_ROUND_UP(refresh, (1000 * 1000)); /* apply scale */ in s3c2410_cpufreq_setrefresh()
44 refresh = (1 << 11) + 1 - refresh; in s3c2410_cpufreq_setrefresh()
46 s3c_freq_dbg("%s: refresh value %lu\n", __func__, refresh); in s3c2410_cpufreq_setrefresh()
50 refval |= refresh; in s3c2410_cpufreq_setrefresh()
H A Diotiming-s3c2412.c260 u32 refresh; in s3c2412_cpufreq_setrefresh() local
264 /* Reduce both the refresh time (in ns) and the frequency (in MHz) in s3c2412_cpufreq_setrefresh()
267 * This should work for HCLK up to 133MHz and refresh period up in s3c2412_cpufreq_setrefresh()
271 refresh = (cfg->freq.hclk / 100) * (board->refresh / 10); in s3c2412_cpufreq_setrefresh()
272 refresh = DIV_ROUND_UP(refresh, (1000 * 1000)); /* apply scale */ in s3c2412_cpufreq_setrefresh()
273 refresh &= ((1 << 16) - 1); in s3c2412_cpufreq_setrefresh()
275 s3c_freq_dbg("%s: refresh value %u\n", __func__, (unsigned int)refresh); in s3c2412_cpufreq_setrefresh()
277 __raw_writel(refresh, S3C2412_REFRESH); in s3c2412_cpufreq_setrefresh()
/OK3568_Linux_fs/external/xserver/hw/xquartz/
H A DquartzRandR.c72 pMode->refresh = (int)(CGDisplayModeGetRefreshRate(modeRef) + 0.5); in QuartzRandRGetModeInfo()
73 if (pMode->refresh == 0) in QuartzRandRGetModeInfo()
74 pMode->refresh = DEFAULT_REFRESH; in QuartzRandRGetModeInfo()
208 (pMode1->refresh == pMode2->refresh); in QuartzRandRModesEqual()
224 …: %d x %d @ %d %s\n", (int)pMode->width, (int)pMode->height, (int)pMode->refresh, isCurrentMode ? … in QuartzRandRRegisterMode()
225 RRRegisterRate(pScreen, pMode->pSize, pMode->refresh); in QuartzRandRRegisterMode()
228 RRSetCurrentConfig(pScreen, RR_Rotate_0, pMode->refresh, in QuartzRandRRegisterMode()
255 (pMode->refresh != FAKE_REFRESH_FULLSCREEN && pMode->refresh != in QuartzRandRSetMode()
287 QuartzSetRootless(pMode->refresh == FAKE_REFRESH_ROOTLESS); in QuartzRandRSetMode()
288 if (pMode->refresh != FAKE_REFRESH_ROOTLESS) { in QuartzRandRSetMode()
[all …]
/OK3568_Linux_fs/kernel/drivers/cpufreq/
H A Dsa1110-cpufreq.c40 u_short refresh; /* refresh time for array (us) */ member
57 .refresh = 64000,
66 .refresh = 64000,
75 .refresh = 64000,
83 .refresh = 64000,
92 .refresh = 64000,
101 .refresh = 64000,
110 .refresh = 64000,
196 * Set the SDRAM refresh rate.
205 * Update the refresh period. We do this such that we always refresh
[all …]
/OK3568_Linux_fs/u-boot/arch/arm/cpu/arm926ejs/lpc32xx/
H A Ddram.c35 /* Select maximum EMC Dynamic Memory Refresh Time */ in ddr_init()
36 writel(0x7FF, &emc->refresh); in ddr_init()
55 /* Dynamic refresh */ in ddr_init()
56 writel((((ck / dram->refresh) >> 4) & 0x7FF), &emc->refresh); in ddr_init()
63 /* Fast dynamic refresh for at least a few SDRAM ck cycles */ in ddr_init()
64 writel((((128) >> 4) & 0x7FF), &emc->refresh); in ddr_init()
66 /* set correct dynamic refresh timing */ in ddr_init()
67 writel((((ck / dram->refresh) >> 4) & 0x7FF), &emc->refresh); in ddr_init()
/OK3568_Linux_fs/kernel/arch/arm/mach-lpc32xx/
H A Dsuspend.S65 @ Setup self-refresh with support for manual exit of
66 @ self-refresh mode
72 @ Wait for self-refresh acknowledge, clocks to the DRAM device
73 @ will automatically stop on start of self-refresh
78 bne 3b @ Branch until self-refresh mode starts
115 @ Re-enter run mode with self-refresh flag cleared, but no DRAM
116 @ update yet. DRAM is still in self-refresh
124 @ Clear self-refresh mode
131 @ Wait for EMC to clear self-refresh mode
135 bne 5b @ Branch until self-refresh has exited
/OK3568_Linux_fs/yocto/meta-rockchip/recipes-graphics/wayland/weston_10.0.2/
H A D0033-backend-drm-Support-setting-interlaced-mode.patch45 m->refresh / 1000.0,
62 (output->base.current_mode->refresh == target_mode->refresh ||
63 target_mode->refresh == 0)) {
73 if (mode->base.refresh == target_mode->refresh ||
74 target_mode->refresh == 0) {
83 uint32_t refresh = 0;
92 &refresh, &aspect_width, &aspect_height);
102 (refresh == 0 || refresh == drm_mode->mode_info.vrefresh)) {
/OK3568_Linux_fs/yocto/meta-rockchip/recipes-graphics/wayland/weston_11.0.1/
H A D0036-backend-drm-Support-setting-interlaced-mode.patch45 m->refresh / 1000.0,
63 (output->base.current_mode->refresh == target_mode->refresh ||
64 target_mode->refresh == 0)) {
74 if (mode->base.refresh == target_mode->refresh ||
75 target_mode->refresh == 0) {
84 uint32_t refresh = 0;
93 &refresh, &aspect_width, &aspect_height);
103 (refresh == 0 || refresh == drm_mode->mode_info.vrefresh)) {
/OK3568_Linux_fs/buildroot/package/weston/
H A D0036-backend-drm-Support-setting-interlaced-mode.patch45 m->refresh / 1000.0,
63 (output->base.current_mode->refresh == target_mode->refresh ||
64 target_mode->refresh == 0)) {
74 if (mode->base.refresh == target_mode->refresh ||
75 target_mode->refresh == 0) {
84 uint32_t refresh = 0;
93 &refresh, &aspect_width, &aspect_height);
103 (refresh == 0 || refresh == drm_mode->mode_info.vrefresh)) {
/OK3568_Linux_fs/kernel/drivers/video/fbdev/core/
H A Dfbcvt.c38 u32 refresh; member
230 cvt->xres, cvt->yres, cvt->refresh); in fb_cvt_print_name()
262 mode->refresh = cvt->f_refresh; in fb_cvt_convert_to_mode()
281 * @mode: pointer to fb_videomode; xres, yres, refresh and vmode must be
288 * @mode is filled with computed values. If interlaced, the refresh field
311 cvt.refresh = mode->refresh; in fb_find_mode_cvt()
312 cvt.f_refresh = cvt.refresh; in fb_find_mode_cvt()
315 if (!cvt.xres || !cvt.yres || !cvt.refresh) { in fb_find_mode_cvt()
320 if (!(cvt.refresh == 50 || cvt.refresh == 60 || cvt.refresh == 70 || in fb_find_mode_cvt()
321 cvt.refresh == 85)) { in fb_find_mode_cvt()
[all …]
H A Dmodedb.c549 mode->xres, mode->yres, bpp, mode->refresh); in fb_try_mode()
590 * <xres>x<yres>[M][R][-<bpp>][@<refresh>][i][p][m]
594 * <name>[-<bpp>][@<refresh>]
596 * with <xres>, <yres>, <bpp> and <refresh> decimal numbers and
599 * If 'M' is present after yres (and before refresh/bpp if present),
613 * 2 if using specified @mode_option with an ignored refresh rate,
644 unsigned int xres = 0, yres = 0, bpp = default_bpp, refresh = 0; in fb_find_mode() local
656 refresh = simple_strtol(&name[i+1], NULL, in fb_find_mode()
723 (refresh) ? refresh : 60, in fb_find_mode()
731 cvt_mode.refresh = (refresh) ? refresh : 60; in fb_find_mode()
[all …]
/OK3568_Linux_fs/kernel/drivers/gpu/drm/
H A Ddrm_self_refresh_helper.c27 * framework to implement panel self refresh (SR) support. Drivers are
32 * (meaning it knows how to initiate self refresh on the panel).
140 * update the average entry/exit self refresh times on self refresh transitions.
142 * entering self refresh mode after activity.
179 * incompatible with self refresh exit and changes them. This is a bit
181 * another. However in order to keep self refresh entirely hidden from
184 * At the end, we queue up the self refresh entry work so we can enter PSR after
227 * drm_self_refresh_helper_init - Initializes self refresh helpers for a crtc
228 * @crtc: the crtc which supports self refresh supported displays
265 * drm_self_refresh_helper_cleanup - Cleans up self refresh helpers for a crtc
/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/dram/
H A Drk3399_dram_timing.txt16 - sr_idle : Defines the Self-Refresh or Self-Refresh with Memory Clock Gating
19 before the controller will automatically issue an entry into the Self-Refresh
20 or Self-Refresh with Memory Clock Gating low power state.
22 - sr_mc_gate_idle : Defined the Self-Refresh with Memory and Controller Clock Gating
25 the controller will automatically issue an entry into the Self-Refresh with
28 - srpd_lite_idle : Define the Lite Self-Refresh Power-Down auto entry periodic
32 Lite Self-Refresh Power-Down low power state.
/OK3568_Linux_fs/u-boot/board/freescale/m5249evb/
H A Dm5249evb.c46 * SO=1, NAM=0, COC=0, RTIM=01 (6clk refresh), RC=39 in dram_init()
52 * SO=1, NAM=0, COC=0, RTIM=01 (6clk refresh), RC=02 in dram_init()
58 * SO=1, NAM=0, COC=0, RTIM=01 (6clk refresh), RC=22 (562 bus clock cycles) in dram_init()
68 /* RE=0 (keep auto-refresh disabled while setting up registers) */ in dram_init()
79 /** Refresh Sequence **/ in dram_init()
80 mbar_writeLong(MCFSIM_DACR0, 0x0000b324); /* Enable the refresh bit, DACR0[RE] (bit 15) */ in dram_init()
81 udelay(0x7d0); /* Allow gobs of refresh cycles */ in dram_init()
/OK3568_Linux_fs/kernel/arch/arm/mach-pxa/
H A Dsleep.S54 @ prepare SDRAM refresh settings
58 @ enable SDRAM self-refresh mode
95 @ prepare SDRAM refresh settings
99 @ enable SDRAM self-refresh mode
107 @ as possible to eliminate messing about with the refresh clock
159 @ external accesses after SDRAM is put in self-refresh mode
160 @ (see Errata 38 ...hangs when entering self-refresh mode)
165 @ put SDRAM into self-refresh
/OK3568_Linux_fs/kernel/arch/arm/mach-socfpga/
H A Dself-refresh.S44 * return value: lower 16 bits: loop count going into self refresh
45 * upper 16 bits: loop count exiting self refresh
53 /* Enable self refresh: set sdr.ctrlgrp.lowpwreq.selfrshreq = 1 */
89 /* Disable self-refresh: set sdr.ctrlgrp.lowpwreq.selfrshreq = 0 */
109 * Shift loop count for exiting self refresh into upper 16 bits.
110 * Leave loop count for requesting self refresh in lower 16 bits.
/OK3568_Linux_fs/u-boot/doc/device-tree-bindings/clock/
H A Drockchip,rk3288-dmc.txt23 …ck frequency high than sr-enable-freq,this driver should enable the automatic self refresh function
25 …refresh-cnt: Self Refresh idle period. Memories are placed into Self-Refresh mode if the NIF is id…
139 rockchip,auto-self-refresh-cnt = <0>;
/OK3568_Linux_fs/u-boot/board/wandboard/
H A Dspl.c190 .refsel = 1, /* Refresh cycles at 32KHz */
191 .refr = 3, /* 4 refresh commands per refresh cycle */
233 .refsel = 1, /* Refresh cycles at 32KHz */
234 .refr = 3, /* 4 refresh commands per refresh cycle */
252 .refsel = 1, /* Refresh cycles at 32KHz */
253 .refr = 3, /* 4 refresh commands per refresh cycle */
/OK3568_Linux_fs/u-boot/arch/arm/include/asm/arch-lpc32xx/
H A Demc.h19 u32 refresh; /* Configures dyn memory refresh operation */ member
24 u32 t_srex; /* Self-refresh exit time */
28 u32 t_rfc; /* Auto-refresh period */
29 u32 t_xsr; /* Exit self-refresh to active command time */
95 u32 refresh; member
/OK3568_Linux_fs/kernel/include/soc/at91/
H A Dat91sam9_sdramc.h26 #define AT91_SDRAMC_TR 0x04 /* SDRAM Controller Refresh Timer Register */
27 #define AT91_SDRAMC_COUNT (0xfff << 0) /* Refresh Timer Counter */
54 #define AT91_SDRAMC_TXSR (0xf << 28) /* Exit Self Refresh to Active Delay */
62 #define AT91_SDRAMC_PASR (7 << 4) /* Partial Array Self Refresh */
63 #define AT91_SDRAMC_TCSR (3 << 8) /* Temperature Compensated Self Refresh */
74 #define AT91_SDRAMC_RES (1 << 0) /* Refresh Error Status */
/OK3568_Linux_fs/kernel/Documentation/fb/
H A Dmodedb.rst23 <xres>x<yres>[M][R][-<bpp>][@<refresh>][i][m][eDd]
24 <name>[-<bpp>][@<refresh>]
26 with <xres>, <yres>, <bpp> and <refresh> decimal numbers and <name> a string.
30 <bpp> and <refresh>, if specified) the timings will be calculated using
81 and coordinated set of standard formats, display refresh rates, and
92 pixelclock, the horizontal sync frequency, or the vertical refresh rate.
127 - acceptable refresh rates are 50, 60, 70 or 85 Hz only
128 - if reduced blanking, the refresh rate must be at 60Hz
152 video=<driver>:<xres>x<yres>[-<bpp>][@refresh]
/OK3568_Linux_fs/kernel/arch/sh/boards/mach-kfr2r09/
H A Dsdram.S3 * KFR2R09 sdram self/auto-refresh setup code
15 /* code to enter and leave self-refresh. must be self-contained.
21 /* DBSC: put memory in self-refresh mode */
37 /* DBSC: put memory in auto-refresh mode */
55 /* DBSC: re-initialize and put in auto-refresh */
/OK3568_Linux_fs/kernel/drivers/gpu/drm/amd/display/modules/freesync/
H A Dfreesync.c36 /* Refresh rate ramp at a fixed rate of 65 Hz/second */
44 /*Threshold to exit fixed refresh rate*/
46 /* Number of consecutive frames to check before entering/exiting fixed refresh*/
200 * standard frame duration (frame duration at 60 Hz refresh rate). in update_v_total_for_static_ramp()
205 /* Going to a higher refresh rate (lower frame duration) */ in update_v_total_for_static_ramp()
218 /* Going to a lower refresh rate (larger frame duration) */ in update_v_total_for_static_ramp()
406 /* Compute the exit refresh rate and exit frame duration */ in apply_fixed_refresh()
412 /* Exit Fixed Refresh mode */ in apply_fixed_refresh()
425 /* Enter Fixed Refresh mode */ in apply_fixed_refresh()
549 /* PB7 = FreeSync Minimum refresh rate (Hz) */ in build_vrr_infopacket_data_v1()
[all …]
/OK3568_Linux_fs/u-boot/include/
H A Dddr_spd.h27 unsigned char refresh; /* 12 Refresh Rate/Type */ member
53 unsigned char trc; /* 41 Min Active to Auto refresh time tRC */
90 unsigned char refresh; /* 12 Refresh Rate/Type */ member
121 unsigned char trc; /* 41 Min Active to Auto refresh time tRC */
150 due to Burst Refresh (DT5B) */
207 unsigned char trc_min_lsb; /* 23 Min Active to Active/Refresh
209 unsigned char trfc_min_lsb; /* 24 Min Refresh Recovery Delay Time */
210 unsigned char trfc_min_msb; /* 25 Min Refresh Recovery Delay Time */
219 unsigned char therm_ref_opt; /* 31 SDRAM Thermal and Refresh Opts */
302 uint8_t thermal_ref; /* 8 Thermal and refresh */
[all …]
/OK3568_Linux_fs/u-boot/arch/arm/mach-at91/include/mach/
H A Dat91sam9_sdramc.h56 #define AT91_SDRAMC_TR (ATMEL_BASE_SDRAMC + 0x04) /* SDRAM Controller Refresh Timer Register */
57 #define AT91_SDRAMC_COUNT (0xfff << 0) /* Refresh Timer Counter */
89 #define AT91_SDRAMC_TXSR (0xf << 28) /* Exit Self Refresh to Active Delay */
98 #define AT91_SDRAMC_PASR (7 << 4) /* Partial Array Self Refresh */
99 #define AT91_SDRAMC_TCSR (3 << 8) /* Temperature Compensated Self Refresh */
110 #define AT91_SDRAMC_RES (1 << 0) /* Refresh Error Status */

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