Searched +full:exynos4210 +full:- +full:pd (Results 1 – 16 of 16) sorted by relevance
1 # SPDX-License-Identifier: GPL-2.03 ---4 $id: http://devicetree.org/schemas/power/pd-samsung.yaml#5 $schema: http://devicetree.org/meta-schemas/core.yaml#10 - Krzysztof Kozlowski <krzk@kernel.org>17 - $ref: power-domain.yaml#22 - samsung,exynos4210-pd23 - samsung,exynos5433-pd32 clock-names:41 "#power-domain-cells":[all …]
1 // SPDX-License-Identifier: GPL-2.05 * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.7 * Copyright (c) 2010-2011 Linaro Ltd.19 #include <dt-bindings/clock/exynos4.h>20 #include <dt-bindings/clock/exynos-audss-clk.h>21 #include <dt-bindings/interrupt-controller/arm-gic.h>22 #include <dt-bindings/interrupt-controller/irq.h>25 interrupt-parent = <&gic>;26 #address-cells = <1>;27 #size-cells = <1>;[all …]
1 // SPDX-License-Identifier: GPL-2.017 #include "exynos4-cpu-thermal.dtsi"18 #include <dt-bindings/clock/exynos3250.h>19 #include <dt-bindings/interrupt-controller/arm-gic.h>20 #include <dt-bindings/interrupt-controller/irq.h>24 interrupt-parent = <&gic>;25 #address-cells = <1>;26 #size-cells = <1>;50 #address-cells = <1>;51 #size-cells = <0>;[all …]
1 // SPDX-License-Identifier: GPL-2.017 #include <dt-bindings/clock/exynos5250.h>19 #include "exynos4-cpu-thermal.dtsi"20 #include <dt-bindings/clock/exynos-audss-clk.h>50 #address-cells = <1>;51 #size-cells = <0>;55 compatible = "arm,cortex-a15";58 clock-names = "cpu";59 operating-points-v2 = <&cpu0_opp_table>;60 #cooling-cells = <2>; /* min followed by max */[all …]
1 // SPDX-License-Identifier: GPL-2.014 #include <dt-bindings/clock/exynos5420.h>15 #include <dt-bindings/clock/exynos-audss-clk.h>16 #include <dt-bindings/interrupt-controller/arm-gic.h>42 * by exynos5420-cpus.dtsi or exynos5422-cpus.dtsi.46 compatible = "operating-points-v2";47 opp-shared;49 opp-1800000000 {50 opp-hz = /bits/ 64 <1800000000>;51 opp-microvolt = <1250000 1250000 1500000>;[all …]
1 // SPDX-License-Identifier: GPL-2.03 * Samsung's Exynos4210 SoC device tree source5 * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.7 * Copyright (c) 2010-2011 Linaro Ltd.10 * Samsung's Exynos4210 SoC device nodes are listed in this file. Exynos421015 * Exynos4210 SoC. As device tree coverage for Exynos4210 increases, additional20 #include "exynos4-cpu-thermal.dtsi"23 compatible = "samsung,exynos4210", "samsung,exynos4";32 #address-cells = <1>;33 #size-cells = <0>;[all …]
1 // SPDX-License-Identifier: GPL-2.020 compatible = "samsung,exynos5800-clock", "syscon";24 opp-2000000000 {25 opp-hz = /bits/ 64 <2000000000>;26 opp-microvolt = <1312500 1312500 1500000>;27 clock-latency-ns = <140000>;29 opp-1900000000 {30 opp-hz = /bits/ 64 <1900000000>;31 opp-microvolt = <1262500 1262500 1500000>;32 clock-latency-ns = <140000>;[all …]
1 // SPDX-License-Identifier: GPL-2.019 #include "exynos4-cpu-thermal.dtsi"29 fimc-lite0 = &fimc_lite_0;30 fimc-lite1 = &fimc_lite_1;35 #address-cells = <1>;36 #size-cells = <0>;40 compatible = "arm,cortex-a9";43 clock-names = "cpu";44 operating-points-v2 = <&cpu0_opp_table>;45 #cooling-cells = <2>; /* min followed by max */[all …]
2 * Samsung's Exynos4210 SoC device tree source4 * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.6 * Copyright (c) 2010-2011 Linaro Ltd.9 * Samsung's Exynos4210 SoC device nodes are listed in this file. Exynos421014 * Exynos4210 SoC. As device tree coverage for Exynos4210 increases, additional23 #include "exynos4210-pinctrl.dtsi"24 #include "exynos4210-pinctrl-uboot.dtsi"27 compatible = "samsung,exynos4210";35 pd_lcd1: lcd1-power-domain@10023CA0 {36 compatible = "samsung,exynos4210-pd";[all …]
21 #include "exynos4x12-pinctrl.dtsi"22 #include "exynos4x12-pinctrl-uboot.dtsi"32 pd_isp: isp-power-domain@10023CA0 {33 compatible = "samsung,exynos4210-pd";37 clock: clock-controller@10030000 {38 compatible = "samsung,exynos4412-clock";40 #clock-cells = <1>;44 compatible = "samsung,exynos4412-mct";46 interrupt-parent = <&mct_map>;49 clock-names = "fin_pll", "mct";[all …]
1 // SPDX-License-Identifier: GPL-2.09 // conjunction with runtime-pm. Support for both device-tree and non-device-tree32 struct generic_pm_domain pd; member38 struct exynos_pm_domain *pd; in exynos_pd_power() local43 pd = container_of(domain, struct exynos_pm_domain, pd); in exynos_pd_power()44 base = pd->base; in exynos_pd_power()46 pwr = power_on ? pd->local_pwr_cfg : 0; in exynos_pd_power()52 while ((readl_relaxed(base + 0x4) & pd->local_pwr_cfg) != pwr) { in exynos_pd_power()55 pr_err("Power domain %s %s failed\n", domain->name, op); in exynos_pd_power()56 return -ETIMEDOUT; in exynos_pd_power()[all …]
1 // SPDX-License-Identifier: GPL-2.05 // Common Clock Framework support for Exynos5 power-domain dependent clocks14 #include "clk-exynos5-subcmu.h"24 for (; num_regs > 0; --num_regs, ++rd) { in exynos5_subcmu_clk_save()25 rd->save = readl(base + rd->offset); in exynos5_subcmu_clk_save()26 writel((rd->save & ~rd->mask) | rd->value, base + rd->offset); in exynos5_subcmu_clk_save()27 rd->save &= rd->mask; in exynos5_subcmu_clk_save()35 for (; num_regs > 0; --num_regs, ++rd) in exynos5_subcmu_clk_restore()36 writel((readl(base + rd->offset) & ~rd->mask) | rd->save, in exynos5_subcmu_clk_restore()37 base + rd->offset); in exynos5_subcmu_clk_restore()[all …]
1 // SPDX-License-Identifier: GPL-2.016 #include <dt-bindings/clock/exynos5433.h>17 #include <dt-bindings/interrupt-controller/arm-gic.h>21 #address-cells = <2>;22 #size-cells = <2>;24 interrupt-parent = <&gic>;27 compatible = "arm,cortex-a53-pmu";32 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;36 compatible = "arm,cortex-a57-pmu";41 interrupt-affinity = <&cpu4>, <&cpu5>, <&cpu6>, <&cpu7>;[all …]
5 force -- enable ACPI if default was off6 on -- enable ACPI but allow fallback to DT [arm64]7 off -- disable ACPI if default was on8 noirq -- do not use ACPI for IRQ routing9 strict -- Be less tolerant of platforms that are not11 rsdt -- prefer RSDT over (default) XSDT12 copy_dsdt -- copy DSDT to memory26 If set to vendor, prefer vendor-specific driver58 Documentation/firmware-guide/acpi/debug.rst for more information about121 Disable auto-serialization of AML methods[all …]
... -boot-2021.07/.readthedocs.yml u-boot-2021.07/Kbuild u-boot-2021.07 ...
9 -------------------------30 ``diff -u`` to make the patch easy to merge. Be prepared to get your40 See Documentation/process/coding-style.rst for guidance here.46 See Documentation/process/submitting-patches.rst for details.57 include a Signed-off-by: line. The current version of this59 Documentation/process/submitting-patches.rst.70 that the bug would present a short-term risk to other users if it76 Documentation/admin-guide/security-bugs.rst for details.81 ---------------------------------------------------97 W: *Web-page* with status/info[all …]