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/OK3568_Linux_fs/external/security/rk_tee_user/v2/host/xtest/
H A Dregression_5000.c1 // SPDX-License-Identifier: GPL-2.0
35 (op)->params[(param_num)].memref.size); \
38 (op)->params[(param_num)].memref.parent); \
40 (shrm)->buffer, \
41 (op)->params[(param_num)].memref.size); \
53 (op)->params[(param_num)].tmpref.size); \
56 (op)->params[(param_num)].tmpref.buffer); \
59 (op)->params[(param_num)].memref.size); \
68 shm->flags = flags; in RegisterSharedMemory()
69 shm->size = size; in RegisterSharedMemory()
[all …]
H A Dregression_1000.c1 // SPDX-License-Identifier: GPL-2.0
51 static void xtest_crypto_test(struct xtest_crypto_session *cs) in xtest_crypto_test() argument
59 Do_ADBG_BeginSubCase(cs->c, "AES encrypt"); in xtest_crypto_test()
71 (void)ADBG_EXPECT_TEEC_SUCCESS(cs->c, in xtest_crypto_test()
72 TEEC_InvokeCommand(cs->session, in xtest_crypto_test()
73 cs-> in xtest_crypto_test()
78 Do_ADBG_EndSubCase(cs->c, "AES encrypt"); in xtest_crypto_test()
80 Do_ADBG_BeginSubCase(cs->c, "AES decrypt"); in xtest_crypto_test()
83 uint8_t out[16] = { }; in xtest_crypto_test() local
87 op.params[1].tmpref.buffer = out; in xtest_crypto_test()
[all …]
/OK3568_Linux_fs/kernel/drivers/misc/habanalabs/common/
H A Dcommand_submission.c1 // SPDX-License-Identifier: GPL-2.0
4 * Copyright 2016-2019 HabanaLabs, Ltd.
25 struct hl_device *hdev = hw_sob->hdev; in hl_sob_reset()
27 hdev->asic_funcs->reset_sob(hdev, hw_sob); in hl_sob_reset()
34 struct hl_device *hdev = hw_sob->hdev; in hl_sob_reset_error()
36 dev_crit(hdev->dev, in hl_sob_reset_error()
38 hw_sob->q_idx, hw_sob->sob_id); in hl_sob_reset_error()
47 struct hl_device *hdev = hl_cs_cmpl->hdev; in hl_fence_release()
49 /* EBUSY means the CS was never submitted and hence we don't have in hl_fence_release()
52 if (fence->error == -EBUSY) in hl_fence_release()
[all …]
H A Dhw_queue.c1 // SPDX-License-Identifier: GPL-2.0
4 * Copyright 2016-2019 HabanaLabs, Ltd.
13 * hl_queue_add_ptr - add to pi or ci and checks if it wraps around
23 ptr &= ((HL_QUEUE_LENGTH << 1) - 1); in hl_hw_queue_add_ptr()
28 return atomic_read(ci) & ((queue_len << 1) - 1); in queue_ci_get()
33 int delta = (q->pi - queue_ci_get(&q->ci, queue_len)); in queue_free_slots()
36 return (queue_len - delta); in queue_free_slots()
38 return (abs(delta) - queue_len); in queue_free_slots()
41 void hl_int_hw_queue_update_ci(struct hl_cs *cs) in hl_int_hw_queue_update_ci() argument
43 struct hl_device *hdev = cs->ctx->hdev; in hl_int_hw_queue_update_ci()
[all …]
/OK3568_Linux_fs/kernel/fs/fuse/
H A Ddev.c3 Copyright (C) 2001-2008 Miklos Szeredi <miklos@szeredi.hu>
38 * Lockless access is OK, because file->private data is set in fuse_get_dev()
41 return READ_ONCE(file->private_data); in fuse_get_dev()
46 INIT_LIST_HEAD(&req->list); in fuse_request_init()
47 INIT_LIST_HEAD(&req->intr_entry); in fuse_request_init()
48 init_waitqueue_head(&req->waitq); in fuse_request_init()
49 refcount_set(&req->count, 1); in fuse_request_init()
50 __set_bit(FR_PENDING, &req->flags); in fuse_request_init()
51 req->fm = fm; in fuse_request_init()
70 refcount_inc(&req->count); in __fuse_get_request()
[all …]
/OK3568_Linux_fs/kernel/drivers/gpu/drm/i915/selftests/
H A Di915_perf.c2 * SPDX-License-Identifier: MIT
17 #define TEST_OA_CONFIG_UUID "12345678-1234-1234-1234-1234567890ab"
26 return -ENOMEM; in alloc_empty_config()
28 oa_config->perf = perf; in alloc_empty_config()
29 kref_init(&oa_config->ref); in alloc_empty_config()
31 strlcpy(oa_config->uuid, TEST_OA_CONFIG_UUID, sizeof(oa_config->uuid)); in alloc_empty_config()
33 mutex_lock(&perf->metrics_lock); in alloc_empty_config()
35 oa_config->id = idr_alloc(&perf->metrics_idr, oa_config, 2, 0, GFP_KERNEL); in alloc_empty_config()
36 if (oa_config->id < 0) { in alloc_empty_config()
37 mutex_unlock(&perf->metrics_lock); in alloc_empty_config()
[all …]
H A Di915_request.c20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
73 request = mock_request(rcs0(i915)->kernel_context, HZ / 10); in igt_add_request()
75 return -ENOMEM; in igt_add_request()
87 int err = -EINVAL; in igt_wait_request()
91 request = mock_request(rcs0(i915)->kernel_context, T); in igt_wait_request()
93 return -ENOMEM; in igt_wait_request()
97 if (i915_request_wait(request, 0, 0) != -ETIME) { in igt_wait_request()
102 if (i915_request_wait(request, 0, T) != -ETIME) { in igt_wait_request()
114 if (i915_request_wait(request, 0, 0) != -ETIME) { in igt_wait_request()
124 if (i915_request_wait(request, 0, T / 2) != -ETIME) { in igt_wait_request()
[all …]
/OK3568_Linux_fs/kernel/drivers/spi/
H A Dspi-omap2-mcspi.c1 // SPDX-License-Identifier: GPL-2.0-or-later
15 #include <linux/dma-mapping.h>
30 #include <linux/platform_data/spi-omap2-mcspi.h>
47 /* per-channel banks, 0x14 bytes each, first is: */
54 /* per-register bitmasks: */
90 /* We have 2 DMA channels per CS, one for RX and one for TX */
115 struct list_head cs; member
149 writel_relaxed(val, mcspi->base + idx); in mcspi_write_reg()
156 return readl_relaxed(mcspi->base + idx); in mcspi_read_reg()
162 struct omap2_mcspi_cs *cs = spi->controller_state; in mcspi_write_cs_reg() local
[all …]
/OK3568_Linux_fs/kernel/drivers/gpu/drm/i915/gt/
H A Dselftest_lrc.c2 * SPDX-License-Identifier: MIT
24 #define CS_GPR(engine, n) ((engine)->mmio_base + 0x600 + (n) * 4)
34 obj = i915_gem_object_create_internal(gt->i915, PAGE_SIZE); in create_scratch()
40 vma = i915_vma_instance(obj, &gt->ggtt->vm, NULL); in create_scratch()
82 if (!READ_ONCE(engine->execlists.pending[0]) && is_active(rq)) in wait_for_submit()
86 return -ETIME; in wait_for_submit()
102 if (READ_ONCE(engine->execlists.pending[0])) in wait_for_reset()
108 if (READ_ONCE(rq->fence.error)) in wait_for_reset()
114 if (rq->fence.error != -EIO) { in wait_for_reset()
116 engine->name, in wait_for_reset()
[all …]
H A Dselftest_engine_cs.c2 * SPDX-License-Identifier: GPL-2.0
21 return *a - *b; in cmp_u32()
29 atomic_inc(&gt->rps.num_waiters); in perf_begin()
30 schedule_work(&gt->rps.work); in perf_begin()
31 flush_work(&gt->rps.work); in perf_begin()
36 atomic_dec(&gt->rps.num_waiters); in perf_end()
39 return igt_flush_test(gt->i915); in perf_end()
45 u32 *cs; in write_timestamp() local
47 cs = intel_ring_begin(rq, 4); in write_timestamp()
48 if (IS_ERR(cs)) in write_timestamp()
[all …]
H A Dintel_ring_submission.c2 * Copyright © 2008-2010 Intel Corporation
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
44 * set-context and then emitting the batch.
54 if (engine->class == RENDER_CLASS) { in set_hwstam()
55 if (INTEL_GEN(engine->i915) >= 6) in set_hwstam()
69 if (INTEL_GEN(engine->i915) >= 4) in set_hws_pga()
72 intel_uncore_write(engine->uncore, HWS_PGA, addr); in set_hws_pga()
77 struct drm_i915_gem_object *obj = engine->status_page.vma->obj; in status_page()
80 return sg_page(obj->mm.pages->sgl); in status_page()
97 if (IS_GEN(engine->i915, 7)) { in set_hwsp()
[all …]
H A Dselftest_ring_submission.c1 // SPDX-License-Identifier: MIT
13 u32 *cs; in create_wally() local
16 obj = i915_gem_object_create_internal(engine->i915, 4096); in create_wally()
20 vma = i915_vma_instance(obj, engine->gt->vm, NULL); in create_wally()
38 cs = i915_gem_object_pin_map(obj, I915_MAP_WC); in create_wally()
39 if (IS_ERR(cs)) { in create_wally()
41 return ERR_CAST(cs); in create_wally()
44 if (INTEL_GEN(engine->i915) >= 6) { in create_wally()
45 *cs++ = MI_STORE_DWORD_IMM_GEN4; in create_wally()
46 *cs++ = 0; in create_wally()
[all …]
H A Dselftest_timeline.c2 * SPDX-License-Identifier: MIT
4 * Copyright © 2017-2018 Intel Corporation
26 struct drm_i915_gem_object *obj = tl->hwsp_ggtt->obj; in hwsp_page()
29 return sg_page(obj->mm.pages->sgl); in hwsp_page()
36 return (address + tl->hwsp_offset) / CACHELINE_BYTES; in hwsp_cacheline()
57 tl = xchg(&state->history[idx], tl); in __mock_hwsp_record()
59 radix_tree_delete(&state->cachelines, hwsp_cacheline(tl)); in __mock_hwsp_record()
71 while (count--) { in __mock_hwsp_timeline()
75 tl = intel_timeline_create(state->gt); in __mock_hwsp_timeline()
80 err = radix_tree_insert(&state->cachelines, cacheline, tl); in __mock_hwsp_timeline()
[all …]
H A Dselftest_rc6.c2 * SPDX-License-Identifier: MIT
34 struct intel_rc6 *rc6 = &gt->rc6; in live_rc6_manual()
46 if (!rc6->enabled) in live_rc6_manual()
50 if (IS_VALLEYVIEW(gt->i915) || IS_CHERRYVIEW(gt->i915)) in live_rc6_manual()
53 wakeref = intel_runtime_pm_get(gt->uncore->rpm); in live_rc6_manual()
64 rc0_power = librapl_energy_uJ() - rc0_power; in live_rc6_manual()
67 if ((res[1] - res[0]) >> 10) { in live_rc6_manual()
69 (res[1] - res[0]) >> 10); in live_rc6_manual()
70 err = -EINVAL; in live_rc6_manual()
77 err = -EINVAL; in live_rc6_manual()
[all …]
/OK3568_Linux_fs/kernel/drivers/staging/kpc2000/
H A Dkpc2000_spi.c1 // SPDX-License-Identifier: GPL-2.0+
5 * Copyright (C) 2014-2018 Daktronics
7 * Very loosely based on spi-omap2-mcspi.c
13 #include <linux/io-64-nonatomic-lo-hi.h>
126 unsigned int cs : 4; /* Chip Select */ member
163 kp_spi_read_reg(struct kp_spi_controller_state *cs, int idx) in kp_spi_read_reg() argument
165 u64 __iomem *addr = cs->base; in kp_spi_read_reg()
168 if ((idx == KP_SPI_REG_CONFIG) && (cs->conf_cache >= 0)) in kp_spi_read_reg()
169 return cs->conf_cache; in kp_spi_read_reg()
175 kp_spi_write_reg(struct kp_spi_controller_state *cs, int idx, u64 val) in kp_spi_write_reg() argument
[all …]
/OK3568_Linux_fs/u-boot/drivers/spi/
H A Domap3_spi.c8 * Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/
17 * SPDX-License-Identifier: GPL-2.0+
44 /* per-register bitmasks */
105 /* channel0: 0x2C - 0x3C, bus 0 & 1 & 2 & 3 */
106 /* channel1: 0x40 - 0x50, bus 0 & 1 */
107 /* channel2: 0x54 - 0x64, bus 0 & 1 */
108 /* channel3: 0x68 - 0x78, bus 0 */
116 unsigned int cs; member
125 writel(val, &priv->regs->channel[priv->cs].chconf); in omap3_spi_write_chconf()
127 readl(&priv->regs->channel[priv->cs].chconf); in omap3_spi_write_chconf()
[all …]
H A Datmel_spi.c4 * SPDX-License-Identifier: GPL-2.0+
45 struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs, in spi_setup_slave() argument
53 if (!spi_cs_is_valid(bus, cs)) in spi_setup_slave()
80 scbr = (get_spi_clk_rate(bus) + max_hz - 1) / max_hz; in spi_setup_slave()
94 as = spi_alloc_slave(struct atmel_spi_slave, bus, cs); in spi_setup_slave()
98 as->regs = regs; in spi_setup_slave()
99 as->mr = ATMEL_SPI_MR_MSTR | ATMEL_SPI_MR_MODFDIS in spi_setup_slave()
100 | ATMEL_SPI_MR_PCS(~(1 << cs) & 0xf); in spi_setup_slave()
102 as->mr |= ATMEL_SPI_MR_WDRBT; in spi_setup_slave()
104 spi_writel(as, CSR(cs), csrx); in spi_setup_slave()
[all …]
H A Ddavinci_spi.c2 * Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/
9 * SPDX-License-Identifier: GPL-2.0+
60 * driver. Platform can configure number of CS using CONFIG_SYS_SPI0_NUM_CS
61 * if more than one CS is supported and by defining CONFIG_SYS_SPI0.
70 * define CONFIG_SYS_SPI1 when platform has spi-1 device (bus #1) and
71 * CONFIG_SYS_SPI1_NUM_CS defines number of CS on this bus
80 * define CONFIG_SYS_SPI2 when platform has spi-2 device (bus #2) and
81 * CONFIG_SYS_SPI2_NUM_CS defines number of CS on this bus
128 u8 num_cs; /* total no. of CS available */
129 u8 cur_cs; /* CS of current slave */
[all …]
/OK3568_Linux_fs/kernel/kernel/cgroup/
H A Dcpuset.c7 * Copyright (C) 2004-2007 Silicon Graphics, Inc.
11 * sysfs is Copyright (c) 2001-3 Patrick Mochel
13 * 2003-10-10 Written by Simon Derr.
14 * 2003-10-22 Updates by Stephen Hemminger.
15 * 2004 May-July Rework by Paul Jackson.
60 #include <linux/backing-dev.h>
93 * The user-configured masks can only be changed by writing to
107 * The user-configured masks are always the same with effective masks.
110 /* user-configured CPUs and Memory Nodes allow to tasks */
120 * CPUs allocated to child sub-partitions (default hierarchy only)
[all …]
/OK3568_Linux_fs/u-boot/examples/standalone/
H A Drkspi.c4 * SPDX-License-Identifier: GPL-2.0+
48 debug("ctrl0: \t\t0x%08x\n", readl(&regs->ctrlr0)); in rkspi_dump_regs()
49 debug("ctrl1: \t\t0x%08x\n", readl(&regs->ctrlr1)); in rkspi_dump_regs()
50 debug("ssienr: \t\t0x%08x\n", readl(&regs->enr)); in rkspi_dump_regs()
51 debug("ser: \t\t0x%08x\n", readl(&regs->ser)); in rkspi_dump_regs()
52 debug("baudr: \t\t0x%08x\n", readl(&regs->baudr)); in rkspi_dump_regs()
53 debug("txftlr: \t\t0x%08x\n", readl(&regs->txftlr)); in rkspi_dump_regs()
54 debug("rxftlr: \t\t0x%08x\n", readl(&regs->rxftlr)); in rkspi_dump_regs()
55 debug("txflr: \t\t0x%08x\n", readl(&regs->txflr)); in rkspi_dump_regs()
56 debug("rxflr: \t\t0x%08x\n", readl(&regs->rxflr)); in rkspi_dump_regs()
[all …]
/OK3568_Linux_fs/kernel/drivers/gpu/drm/i915/gvt/
H A Dmmio_context.c2 * Copyright(c) 2011-2016 Intel Corporation. All rights reserved.
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
162 struct intel_gvt *gvt = engine->i915->gvt; in load_render_mocs()
163 struct intel_uncore *uncore = engine->uncore; in load_render_mocs()
164 u32 cnt = gvt->engine_mmio_list.mocs_mmio_offset_list_cnt; in load_render_mocs()
165 u32 *regs = gvt->engine_mmio_list.mocs_mmio_offset_list; in load_render_mocs()
174 if (!HAS_ENGINE(engine->gt, ring_id)) in load_render_mocs()
198 u32 *cs; in restore_context_mmio_for_inhibit() local
201 struct intel_gvt *gvt = vgpu->gvt; in restore_context_mmio_for_inhibit()
202 int ring_id = req->engine->id; in restore_context_mmio_for_inhibit()
[all …]
/OK3568_Linux_fs/u-boot/drivers/video/
H A Dhitachi_tx18d42vm_lcd.c6 * SPDX-License-Identifier: GPL-2.0+
19 static void lcd_panel_spi_write(int cs, int clk, int mosi, in lcd_panel_spi_write() argument
24 gpio_direction_output(cs, 0); in lcd_panel_spi_write()
27 offset = (bits - 1) - i; in lcd_panel_spi_write()
33 gpio_direction_output(cs, 1); in lcd_panel_spi_write()
49 int i, cs, clk, mosi, ret = 0; in hitachi_tx18d42vm_init() local
51 cs = name_to_gpio(CONFIG_VIDEO_LCD_SPI_CS); in hitachi_tx18d42vm_init()
55 if (cs == -1 || clk == -1 || mosi == 1) { in hitachi_tx18d42vm_init()
57 return -EINVAL; in hitachi_tx18d42vm_init()
60 if (gpio_request(cs, "tx18d42vm-spi-cs") != 0 || in hitachi_tx18d42vm_init()
[all …]
/OK3568_Linux_fs/kernel/arch/arm64/boot/dts/hisilicon/
H A Dhi6220-coresight.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
14 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
17 clock-names = "apb_pclk";
19 out-ports {
22 remote-endpoint =
28 in-ports {
31 remote-endpoint =
39 compatible = "arm,coresight-tmc", "arm,primecell";
42 clock-names = "apb_pclk";
44 in-ports {
[all …]
/OK3568_Linux_fs/kernel/drivers/gpu/drm/i915/gem/selftests/
H A Di915_gem_coherency.c2 * SPDX-License-Identifier: MIT
30 i915_gem_object_lock(ctx->obj, NULL); in cpu_set()
31 err = i915_gem_object_prepare_write(ctx->obj, &needs_clflush); in cpu_set()
33 goto out; in cpu_set()
35 page = i915_gem_object_get_page(ctx->obj, offset >> PAGE_SHIFT); in cpu_set()
48 i915_gem_object_finish_access(ctx->obj); in cpu_set()
50 out: in cpu_set()
51 i915_gem_object_unlock(ctx->obj); in cpu_set()
63 i915_gem_object_lock(ctx->obj, NULL); in cpu_get()
64 err = i915_gem_object_prepare_read(ctx->obj, &needs_clflush); in cpu_get()
[all …]
/OK3568_Linux_fs/u-boot/include/
H A Dspi.h2 * Common SPI Interface: Controller-specific definitions
7 * SPDX-License-Identifier: GPL-2.0+
22 #define SPI_CS_HIGH BIT(2) /* CS active high */
23 #define SPI_LSB_FIRST BIT(3) /* per-word bits-on-wire */
44 * struct dm_spi_bus - SPI bus info
62 * struct dm_spi_platdata - platform data for all SPI slaves
66 * dev_get_parent_platdata(slave->dev).
71 * @cs: Chip select number (0..n-1)
76 unsigned int cs; member
82 * struct spi_slave - Representation of a SPI slave
[all …]

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