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/optee_os/core/arch/riscv/kernel/
H A Dentry.S147 #ifdef CFG_CORE_ASLR
239 #ifdef CFG_CORE_ASLR
251 #ifdef CFG_CORE_ASLR
261 #ifdef CFG_CORE_ASLR
429 #if defined(CFG_CORE_ASLR)
484 * addresses are identical. When CFG_CORE_ASLR=y:
503 #ifdef CFG_CORE_ASLR
H A Dboot.c240 #ifdef CFG_CORE_ASLR in boot_init_primary_runtime()
292 #if defined(CFG_CORE_ASLR)
317 #endif /*CFG_CORE_ASLR*/
H A Dkern.ld.S111 #ifndef CFG_CORE_ASLR
135 #if defined(CFG_CORE_ASLR)
254 #ifndef CFG_CORE_ASLR
H A Dlink.mk12 ifeq ($(CFG_CORE_ASLR),y)
/optee_os/core/arch/arm/plat-rzg/
H A Dconf.mk16 # 2. OP-TEE crashes during boot with enabled CFG_CORE_ASLR.
17 $(call force,CFG_CORE_ASLR,n)
/optee_os/core/arch/arm/plat-rcar/
H A Dromapi_call.S31 #ifdef CFG_CORE_ASLR
48 #ifdef CFG_CORE_ASLR
/optee_os/core/arch/arm/plat-zynqmp/
H A Dconf.mk14 # 2. OP-TEE does not boot with enabled CFG_CORE_ASLR.
15 $(call force,CFG_CORE_ASLR,n)
/optee_os/core/arch/arm/kernel/
H A Dkern.ld.S125 #ifndef CFG_CORE_ASLR
134 #if defined(CFG_CORE_ASLR)
332 #ifndef CFG_CORE_ASLR
338 #ifdef CFG_CORE_ASLR
447 #if !defined(CFG_CORE_ASLR) && !defined(CFG_CORE_PHYS_RELOCATABLE)
H A Dentry_a32.S583 #ifdef CFG_CORE_ASLR
595 #ifdef CFG_CORE_ASLR
625 #ifdef CFG_CORE_ASLR
855 #ifdef CFG_CORE_ASLR
970 /* r2 = load_offset (always 0 if CFG_CORE_ASLR=n) */
1103 #ifdef CFG_CORE_ASLR
1108 #ifdef CFG_CORE_ASLR
H A Dboot.c423 * With CFG_CORE_ASLR=y the init part is relocated very early during boot.
431 * If CFG_CORE_ASLR=n, nothing needs to be done as the code/ro pages are
436 #ifdef CFG_CORE_ASLR in undo_init_relocation()
463 #ifdef CFG_CORE_ASLR in ro_paged_alloc()
1051 #ifdef CFG_CORE_ASLR in boot_init_primary_runtime()
1237 #if defined(CFG_CORE_ASLR)
1285 #endif /*CFG_CORE_ASLR*/
H A Dentry_a64.S419 #ifdef CFG_CORE_ASLR
431 #ifdef CFG_CORE_ASLR
454 #ifdef CFG_CORE_ASLR
650 #if defined(CFG_CORE_ASLR) || defined(CFG_CORE_PHYS_RELOCATABLE)
H A Dthread_optee_smc_a64.S29 #ifdef CFG_CORE_ASLR
H A Dthread_optee_smc_a32.S31 #ifdef CFG_CORE_ASLR
H A Dlink.mk18 ifeq ($(call cfg-one-enabled, CFG_CORE_ASLR CFG_CORE_PHYS_RELOCATABLE),y)
/optee_os/core/arch/arm/plat-versal/
H A Dconf.mk19 $(call force,CFG_CORE_ASLR,n)
/optee_os/core/arch/riscv/plat-spike/
H A Dconf.mk11 $(call force,CFG_CORE_ASLR,n)
/optee_os/.github/workflows/
H A Dci.yml294 _make CFG_CORE_SANITIZE_KADDRESS=y CFG_CORE_ASLR=n
414 make -j$(nproc) check CFG_CORE_SANITIZE_KADDRESS=y CFG_CORE_ASLR=n CFG_ATTESTATION_PTA=n XTEST_ARGS="n_1001 n_1003 n_1004"
417 make -j$(nproc) check CFG_CORE_SANITIZE_KADDRESS=y CFG_CORE_ASLR=n CFG_ATTESTATION_PTA=n CFG_DYN_CONFIG=n XTEST_ARGS="n_1001 n_1003 n_1004"
537 make -j$(nproc) check CFG_CORE_SANITIZE_KADDRESS=y CFG_CORE_ASLR=n CFG_ATTESTATION_PTA=n RUST_ENABLE=n MEASURED_BOOT_FTPM=n XTEST_ARGS="n_1001 n_1003 n_1004"
/optee_os/core/arch/arm/plat-stm32mp2/
H A Dconf.mk134 CFG_CORE_ASLR ?= n
/optee_os/core/mm/
H A Dfobj.c509 #ifdef CFG_CORE_ASLR
685 #endif /*CFG_CORE_ASLR*/
/optee_os/lib/libutils/ext/include/
H A Dcompiler.h79 #ifdef CFG_CORE_ASLR
/optee_os/core/arch/riscv/
H A Driscv.mk168 ifeq ($(CFG_CORE_ASLR),y)
/optee_os/core/arch/arm/plat-stm32mp1/
H A Dconf.mk179 CFG_CORE_ASLR ?= n
/optee_os/mk/
H A Dconfig.mk338 CFG_CORE_ASLR ?= y
477 ifeq (y-y,$(CFG_CORE_SANITIZE_KADDRESS)-$(CFG_CORE_ASLR))
478 $(error CFG_CORE_SANITIZE_KADDRESS and CFG_CORE_ASLR are not compatible)
/optee_os/core/arch/arm/
H A Darm.mk263 ifeq ($(call cfg-one-enabled, CFG_CORE_ASLR CFG_CORE_PHYS_RELOCATABLE),y)
/optee_os/core/arch/arm/mm/
H A Dcore_mmu_v7.c188 #ifdef CFG_CORE_ASLR

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