1*4055cfc4SLad PrabhakarPLATFORM_FLAVOR ?= hihope_rzg2m 2*4055cfc4SLad Prabhakar 3*4055cfc4SLad Prabhakarinclude core/arch/arm/cpu/cortex-armv8-0.mk 4*4055cfc4SLad Prabhakar 5*4055cfc4SLad Prabhakar$(call force,CFG_SECURE_TIME_SOURCE_CNTPCT,y) 6*4055cfc4SLad Prabhakar$(call force,CFG_WITH_ARM_TRUSTED_FW,y) 7*4055cfc4SLad Prabhakar$(call force,CFG_SCIF,y) 8*4055cfc4SLad Prabhakar$(call force,CFG_CORE_LARGE_PHYS_ADDR,y) 9*4055cfc4SLad Prabhakar$(call force,CFG_CORE_ARM64_PA_BITS,36) 10*4055cfc4SLad Prabhakar 11*4055cfc4SLad Prabhakar# Disable core ASLR for two reasons: 12*4055cfc4SLad Prabhakar# 1. There is no source for ALSR seed, as RZ/G2 platform 13*4055cfc4SLad Prabhakar# does not provide DTB to OP-TEE. Also, there is no 14*4055cfc4SLad Prabhakar# publicly available documentation on integrated 15*4055cfc4SLad Prabhakar# hardware RNG, so we can't use it either. 16*4055cfc4SLad Prabhakar# 2. OP-TEE crashes during boot with enabled CFG_CORE_ASLR. 17*4055cfc4SLad Prabhakar$(call force,CFG_CORE_ASLR,n) 18*4055cfc4SLad Prabhakar 19*4055cfc4SLad Prabhakarifeq ($(PLATFORM_FLAVOR),ek874) 20*4055cfc4SLad Prabhakar$(call force,CFG_TEE_CORE_NB_CORE,2) 21*4055cfc4SLad Prabhakarendif 22*4055cfc4SLad Prabhakarifeq ($(PLATFORM_FLAVOR),hihope_rzg2m) 23*4055cfc4SLad Prabhakar$(call force,CFG_TEE_CORE_NB_CORE,6) 24*4055cfc4SLad Prabhakar# RZ/G2M have 6 cores for 2 clusters, but the number isn't contiguous. 25*4055cfc4SLad Prabhakar# One cluster has ids 0, 1, other has ids 3, 4, 5, 6. 26*4055cfc4SLad Prabhakar# CFG_CORE_CLUSTER_SHIFT will process to make the right numbering. 27*4055cfc4SLad Prabhakar$(call force,CFG_CORE_CLUSTER_SHIFT,1) 28*4055cfc4SLad Prabhakarendif 29*4055cfc4SLad Prabhakarifeq ($(PLATFORM_FLAVOR),hihope_rzg2n) 30*4055cfc4SLad Prabhakar$(call force,CFG_TEE_CORE_NB_CORE,2) 31*4055cfc4SLad Prabhakarendif 32*4055cfc4SLad Prabhakarifeq ($(PLATFORM_FLAVOR),hihope_rzg2h) 33*4055cfc4SLad Prabhakar$(call force,CFG_TEE_CORE_NB_CORE,8) 34*4055cfc4SLad Prabhakarendif 35*4055cfc4SLad Prabhakar 36*4055cfc4SLad PrabhakarCFG_TZDRAM_START ?= 0x44100000 37*4055cfc4SLad PrabhakarCFG_TZDRAM_SIZE ?= 0x03D00000 38*4055cfc4SLad PrabhakarCFG_TEE_RAM_VA_SIZE ?= 0x100000 39*4055cfc4SLad Prabhakarifeq ($(CFG_ARM64_core),y) 40*4055cfc4SLad Prabhakarsupported-ta-targets = ta_arm64 41*4055cfc4SLad Prabhakarendif 42*4055cfc4SLad Prabhakar 43*4055cfc4SLad PrabhakarCFG_DT ?= y 44