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/OK3568_Linux_fs/u-boot/arch/arm/mach-omap2/omap5/
H A Dhw_data.c33 {200, 2, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
34 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
35 {1000, 20, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
36 {375, 8, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
37 {400, 12, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
38 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
39 {375, 17, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */
44 {250, 2, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
45 {500, 9, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 20 MHz */
46 {119, 1, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
[all …]
/OK3568_Linux_fs/u-boot/arch/arm/mach-omap2/omap4/
H A Dhw_data.c37 * dpll locked at 1400 MHz MPU clk at 700 MHz(OPP100) - DCC OFF
41 {175, 2, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
42 {700, 12, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
43 {125, 2, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
44 {401, 10, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
45 {350, 12, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
46 {700, 26, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
47 {638, 34, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */
51 * dpll locked at 1600 MHz - MPU clk at 800 MHz(OPP Turbo 4430)
56 {200, 2, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
[all …]
/OK3568_Linux_fs/kernel/drivers/clk/spear/
H A Dspear1340_clock.c24 #define SPEAR1340_HCLK_SRC_SEL_MASK 1
31 #define SPEAR1340_CLCD_SYNT_CLK_MASK 1
51 #define SPEAR1340_SPDIF_CLK_MASK 1
56 #define SPEAR1340_GPT_CLK_MASK 1
64 #define SPEAR1340_C3_CLK_MASK 1
65 #define SPEAR1340_C3_CLK_SHIFT 1
68 #define SPEAR1340_GMAC_PHY_CLK_MASK 1
86 #define SPEAR1340_I2S_REF_SEL_MASK 1
131 #define SPEAR1340_SYSROM_CLK_ENB 1
142 #define SPEAR1340_DDR_CORE_CLK_ENB 1
[all …]
/OK3568_Linux_fs/kernel/Documentation/fb/
H A Dviafb.modes10 # 640x480, 60 Hz, Non-Interlaced (25.175 MHz dotclock)
29 # D: 25.175 MHz, H: 31.469 kHz, V: 59.94 Hz
32 # D: 24.823 MHz, H: 39.780 kHz, V: 60.00 Hz
33 geometry 480 640 480 640 32 timings 39722 72 24 19 1 48 3 endmode
35 # 640x480, 75 Hz, Non-Interlaced (31.50 MHz dotclock)
43 # 2 chars 1 lines
53 # D: 31.50 MHz, H: 37.500 kHz, V: 75.00 Hz
54 geometry 640 480 640 480 32 timings 31747 120 16 16 1 64 3 endmode
56 # 640x480, 85 Hz, Non-Interlaced (36.000 MHz dotclock)
64 # 7 chars 1 lines
[all …]
/OK3568_Linux_fs/external/rkwifibt/drivers/bcmdhd/
H A Dbcmwifi_channels.c51 /* Definitions for D11AC capable (80MHz+) Chanspec type */
56 * ['/'<1st-channel-segment>'-'<2nd-channel-segment>]]
62 * channel number of the 20MHz channel,
63 * or primary 20 MHz channel of 40MHz, 80MHz, 160MHz, 80+80MHz,
64 * 240MHz, 320MHz, or 160+160MHz channels.
68 * 'u' or 'l' (only for 2.4GHz band 40MHz)
70 * For 2.4GHz band 40MHz channels, the same primary channel may be the
71 * upper sideband for one 40MHz channel, and the lower sideband for an
72 * overlapping 40MHz channel. The {u: upper, l: lower} primary sideband
73 * indication disambiguates which 40MHz channel is being specified.
[all …]
/OK3568_Linux_fs/kernel/drivers/net/wireless/rockchip_wlan/rkwifi/bcmdhd/
H A Dbcmwifi_channels.c51 /* Definitions for D11AC capable (80MHz+) Chanspec type */
56 * ['/'<1st-channel-segment>'-'<2nd-channel-segment>]]
62 * channel number of the 20MHz channel,
63 * or primary 20 MHz channel of 40MHz, 80MHz, 160MHz, 80+80MHz,
64 * 240MHz, 320MHz, or 160+160MHz channels.
68 * 'u' or 'l' (only for 2.4GHz band 40MHz)
70 * For 2.4GHz band 40MHz channels, the same primary channel may be the
71 * upper sideband for one 40MHz channel, and the lower sideband for an
72 * overlapping 40MHz channel. The {u: upper, l: lower} primary sideband
73 * indication disambiguates which 40MHz channel is being specified.
[all …]
/OK3568_Linux_fs/kernel/drivers/clk/samsung/
H A Dclk-s3c2410.c57 MUX(FCLK, "fclk", fclk_p, CLKSLOW, 4, 1),
61 { .val = 0, .div = 1 },
62 { .val = 1, .div = 2 },
74 DIV(PCLK, "pclk", "hclk", CLKDIVN, 0, 1),
123 PLL_S3C2410_MPLL_RATE(12 * MHZ, 270000000, 127, 1, 1),
124 PLL_S3C2410_MPLL_RATE(12 * MHZ, 268000000, 126, 1, 1),
125 PLL_S3C2410_MPLL_RATE(12 * MHZ, 266000000, 125, 1, 1),
126 PLL_S3C2410_MPLL_RATE(12 * MHZ, 226000000, 105, 1, 1),
127 PLL_S3C2410_MPLL_RATE(12 * MHZ, 210000000, 132, 2, 1),
129 PLL_S3C2410_MPLL_RATE(12 * MHZ, 202800000, 161, 3, 1),
[all …]
/OK3568_Linux_fs/u-boot/board/freescale/common/
H A Didt8t49n222a_serdes_clk.c17 ret = i2c_read(idt_addr, 0x17, 1, &val, 1); in check_pll_status()
28 return -1; in check_pll_status()
44 ret = i2c_read(idt_addr, DEVICE_ID_REG, 1, &dev_id, 1); in set_serdes_refclk()
56 if (serdes_num != 1 && serdes_num != 2) { in set_serdes_refclk()
57 debug("serdes_num should be 1 for SerDes1 and" in set_serdes_refclk()
59 return -1; in set_serdes_refclk()
65 debug("Only one refclk at 122.88MHz is not supported." in set_serdes_refclk()
66 " Please set both refclk1 & refclk2 to 122.88MHz" in set_serdes_refclk()
67 " or both not to 122.88MHz.\n"); in set_serdes_refclk()
68 return -1; in set_serdes_refclk()
[all …]
/OK3568_Linux_fs/kernel/drivers/net/wireless/rockchip_wlan/cywdhd/bcmdhd/
H A Dbcmwifi_channels.c59 /* Definitions for D11AC capable (80MHz+) Chanspec type */
62 * [<band> 'g'] <channel> ['/'<bandwidth> [<primary-sideband>]['/'<1st80channel>'-'<2nd80channel>]]
68 * channel number of the 5MHz, 10MHz, 20MHz channel,
69 * or primary channel of 40MHz, 80MHz, 160MHz, or 80+80MHz channel.
73 * (only for 2.4GHz band 40MHz) U for upper sideband primary, L for lower.
75 * For 2.4GHz band 40MHz channels, the same primary channel may be the
76 * upper sideband for one 40MHz channel, and the lower sideband for an
77 * overlapping 40MHz channel. The U/L disambiguates which 40MHz channel
80 * For 40MHz in the 5GHz band and all channel bandwidths greater than
81 * 40MHz, the U/L specificaion is not allowed since the channels are
[all …]
H A Dbcmwifi_channels.h37 /* A chanspec holds the channel number, band, bandwidth and primary 20MHz sideband */
48 #define CH_5MHZ_APART 1 /* 2G band channels are 5 Mhz apart */
50 #define CH_MIN_2G_CHANNEL 1u /* Min channel in 2G band */
52 #define CH_MIN_2G_40M_CHANNEL 3u /* Min 40MHz center channel in 2G band */
53 #define CH_MAX_2G_40M_CHANNEL 11u /* Max 40MHz center channel in 2G band */
55 #define CH_MIN_6G_CHANNEL 1u /* Min channel in 6G band */
137 /* pass a 80MHz channel number (uint8) to get respective LL, UU, LU, UL */
176 #define CHSPEC_IS20(chspec) 1
219 /* pass a center channel and get channel offset from it by 10MHz */
227 /* pass a 160MHz center channel to get 20MHz subband channel numbers */
[all …]
/OK3568_Linux_fs/kernel/drivers/net/wireless/rockchip_wlan/infineon/bcmdhd/
H A Dbcmwifi_channels.c59 /* Definitions for D11AC capable (80MHz+) Chanspec type */
62 * [<band> 'g'] <channel> ['/'<bandwidth> [<primary-sideband>]['/'<1st80channel>'-'<2nd80channel>]]
68 * channel number of the 5MHz, 10MHz, 20MHz channel,
69 * or primary channel of 40MHz, 80MHz, 160MHz, or 80+80MHz channel.
73 * (only for 2.4GHz band 40MHz) U for upper sideband primary, L for lower.
75 * For 2.4GHz band 40MHz channels, the same primary channel may be the
76 * upper sideband for one 40MHz channel, and the lower sideband for an
77 * overlapping 40MHz channel. The U/L disambiguates which 40MHz channel
80 * For 40MHz in the 5GHz band and all channel bandwidths greater than
81 * 40MHz, the U/L specificaion is not allowed since the channels are
[all …]
H A Dbcmwifi_channels.h37 /* A chanspec holds the channel number, band, bandwidth and primary 20MHz sideband */
48 #define CH_5MHZ_APART 1 /* 2G band channels are 5 Mhz apart */
50 #define CH_MIN_2G_CHANNEL 1u /* Min channel in 2G band */
52 #define CH_MIN_2G_40M_CHANNEL 3u /* Min 40MHz center channel in 2G band */
53 #define CH_MAX_2G_40M_CHANNEL 11u /* Max 40MHz center channel in 2G band */
55 #define CH_MIN_6G_CHANNEL 1u /* Min channel in 6G band */
137 /* pass a 80MHz channel number (uint8) to get respective LL, UU, LU, UL */
176 #define CHSPEC_IS20(chspec) 1
219 /* pass a center channel and get channel offset from it by 10MHz */
227 /* pass a 160MHz center channel to get 20MHz subband channel numbers */
[all …]
/OK3568_Linux_fs/u-boot/arch/arm/mach-tegra/
H A Dcpu.c46 * T20: 1 GHz
56 { .n = 1000, .m = 13, .p = 0, .cpcon = 12 }, /* OSC: 13.0 MHz */
57 { .n = 625, .m = 12, .p = 0, .cpcon = 8 }, /* OSC: 19.2 MHz */
58 { .n = 1000, .m = 12, .p = 0, .cpcon = 12 }, /* OSC: 12.0 MHz */
59 { .n = 1000, .m = 26, .p = 0, .cpcon = 12 }, /* OSC: 26.0 MHz */
60 { .n = 0, .m = 0, .p = 0, .cpcon = 0 }, /* OSC: 38.4 MHz (N/A) */
61 { .n = 0, .m = 0, .p = 0, .cpcon = 0 }, /* OSC: 48.0 MHz (N/A) */
74 { .n = 923, .m = 10, .p = 0, .cpcon = 12 }, /* OSC: 13.0 MHz */
75 { .n = 750, .m = 12, .p = 0, .cpcon = 8 }, /* OSC: 19.2 MHz */
76 { .n = 600, .m = 6, .p = 0, .cpcon = 12 }, /* OSC: 12.0 MHz */
[all …]
/OK3568_Linux_fs/kernel/drivers/clk/mvebu/
H A Dmv98dx3236.c25 * 0 = 400 MHz 400 MHz 800 MHz
26 * 2 = 667 MHz 667 MHz 2000 MHz
27 * 3 = 800 MHz 800 MHz 1600 MHz
34 * 1 = 667 MHz 667 MHz 2000 MHz
35 * 2 = 400 MHz 400 MHz 400 MHz
36 * 3 = 800 MHz 800 MHz 800 MHz
37 * 5 = 800 MHz 400 MHz 800 MHz
46 /* Tclk = 200MHz, no SaR dependency */ in mv98dx3236_get_tclk_freq()
98 {0, 1}, {3, 1}, {1, 1}, {1, 1},
99 {0, 1}, {1, 1}, {0, 1}, {0, 1},
[all …]
/OK3568_Linux_fs/external/rkwifibt/drivers/infineon/
H A Dbcmwifi_channels.c59 /* Definitions for D11AC capable (80MHz+) Chanspec type */
62 * [<band> 'g'] <channel> ['/'<bandwidth> [<primary-sideband>]['/'<1st80channel>'-'<2nd80channel>]]
68 * channel number of the 5MHz, 10MHz, 20MHz channel,
69 * or primary channel of 40MHz, 80MHz, 160MHz, or 80+80MHz channel.
73 * (only for 2.4GHz band 40MHz) U for upper sideband primary, L for lower.
75 * For 2.4GHz band 40MHz channels, the same primary channel may be the
76 * upper sideband for one 40MHz channel, and the lower sideband for an
77 * overlapping 40MHz channel. The U/L disambiguates which 40MHz channel
80 * For 40MHz in the 5GHz band and all channel bandwidths greater than
81 * 40MHz, the U/L specificaion is not allowed since the channels are
[all …]
H A Dbcmwifi_channels.h37 /* A chanspec holds the channel number, band, bandwidth and primary 20MHz sideband */
48 #define CH_5MHZ_APART 1 /* 2G band channels are 5 Mhz apart */
50 #define CH_MIN_2G_CHANNEL 1u /* Min channel in 2G band */
52 #define CH_MIN_2G_40M_CHANNEL 3u /* Min 40MHz center channel in 2G band */
53 #define CH_MAX_2G_40M_CHANNEL 11u /* Max 40MHz center channel in 2G band */
57 * this is that + 1 rounded up to a multiple of NBBY (8).
60 #define MAXCHANNEL_NUM (MAXCHANNEL - 1) /* max channel number */
134 /* pass a 80MHz channel number (uint8) to get respective LL, UU, LU, UL */
173 #define CHSPEC_IS20(chspec) 1
216 /* pass a center channel and get channel offset from it by 10MHz */
[all …]
/OK3568_Linux_fs/kernel/drivers/net/wireless/rockchip_wlan/rkwifi/bcmdhd_indep_power/
H A Dbcmwifi_channels.c59 * [<band> 'g'] <channel> ['/'<bandwidth> [<ctl-sideband>]['/'<1st80channel>'-'<2nd80channel>]]
65 * channel number of the 5MHz, 10MHz, 20MHz channel,
66 * or primary channel of 40MHz, 80MHz, 160MHz, or 80+80MHz channel.
70 * (only for 2.4GHz band 40MHz) U for upper sideband primary, L for lower.
72 * For 2.4GHz band 40MHz channels, the same primary channel may be the
73 * upper sideband for one 40MHz channel, and the lower sideband for an
74 * overlapping 40MHz channel. The U/L disambiguates which 40MHz channel
77 * For 40MHz in the 5GHz band and all channel bandwidths greater than
78 * 40MHz, the U/L specificaion is not allowed since the channels are
82 * <1st80Channel>:
[all …]
/OK3568_Linux_fs/kernel/arch/x86/kernel/
H A Dtsc_msr.c22 * The frequency numbers in the SDM are e.g. 83.3 MHz, which does not contain a
24 * use a 25 MHz crystal and Cherry Trail uses a 19.2 MHz crystal, the crystal
25 * is the source clk for a root PLL which outputs 1600 and 100 MHz. It is
31 * clock of 100 MHz plus a quotient which gets us as close to the frequency
33 * For the 83.3 MHz example from above this would give us 100 MHz * 5 / 6 =
34 * 83 and 1/3 MHz, which matches exactly what has been measured on actual hw.
80 * 000: 100 * 5 / 6 = 83.3333 MHz
81 * 001: 100 * 1 / 1 = 100.0000 MHz
82 * 010: 100 * 4 / 3 = 133.3333 MHz
83 * 011: 100 * 7 / 6 = 116.6667 MHz
[all …]
/OK3568_Linux_fs/kernel/arch/arm/mach-omap2/
H A Dopp2xxx.h20 * 2430 (iva2.1, NOdsp, mdm)
45 unsigned long dpll_speed; /* dpll: out*xtal*M/(N-1)table_recalc */
48 unsigned long cm_clksel_dsp; /* dsp+iva1 div(2420), iva2.1(2430) */
68 /* 2430 Ratio's, 2430-Ratio Config 1 */
103 #define RB_CLKSEL_L3 (1 << 0)
104 #define RB_CLKSEL_L4 (1 << 5)
105 #define RB_CLKSEL_USB (1 << 25)
109 #define RB_CLKSEL_MPU (1 << 0)
111 #define RB_CLKSEL_DSP (1 << 0)
112 #define RB_CLKSEL_DSP_IF (1 << 5)
[all …]
/OK3568_Linux_fs/u-boot/arch/arm/mach-omap2/omap3/
H A Dlowlevel_init.S35 .word 0xe1600071 @ SMC #1 to call PPA service - hand assembled
160 .word (WKUP_RSM << 1)
199 /* DPLL(1-4) PARAM TABLES */
208 /* 12MHz */
216 /* 13MHz */
224 /* 19.2MHz */
232 /* 26MHz */
240 /* 38.4MHz */
255 /* 12MHz */
263 /* 13MHz */
[all …]
/OK3568_Linux_fs/kernel/drivers/staging/vt6655/
H A Drf.c57 0x03F79000 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 1, Tf = 2412MHz */
58 0x03F79000 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 2, Tf = 2417MHz */
59 0x03E79000 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 3, Tf = 2422MHz */
60 0x03E79000 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 4, Tf = 2427MHz */
61 0x03F7A000 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 5, Tf = 2432MHz */
62 0x03F7A000 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 6, Tf = 2437MHz */
63 0x03E7A000 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 7, Tf = 2442MHz */
64 0x03E7A000 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 8, Tf = 2447MHz */
65 0x03F7B000 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 9, Tf = 2452MHz */
66 0x03F7B000 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 10, Tf = 2457MHz */
[all …]
/OK3568_Linux_fs/kernel/arch/mips/txx9/rbtx4927/
H A Dsetup.c75 writeb(1, rbtx4927_pcireset_addr); in tx4927_pci_setup()
93 writeb(1, rbtx4927_pcireset_addr); in tx4927_pci_setup()
122 writeb(1, rbtx4927_pcireset_addr); in tx4937_pci_setup()
140 writeb(1, rbtx4927_pcireset_addr); in tx4937_pci_setup()
164 gpio_direction_output(15, 1); in rbtx4927_gpio_init()
190 writeb(1, rbtx4927_softresetlock_addr); in toshiba_rbtx4927_restart()
193 while (!(readb(rbtx4927_softresetlock_addr) & 1)) in toshiba_rbtx4927_restart()
197 writeb(1, rbtx4927_softreset_addr); in toshiba_rbtx4927_restart()
231 * ASSUMPTION: PCIDIVMODE is configured for PCI 33MHz or 66MHz. in rbtx4927_clock_init()
234 * PCIDIVMODE[12:11]'s initial value is given by S9[4:3] (ON:0, OFF:1). in rbtx4927_clock_init()
[all …]
/OK3568_Linux_fs/u-boot/drivers/clk/rockchip/
H A Dclk_rv1106.c23 #define DIV_TO_RATE(input_rate, div) ((input_rate) / ((div) + 1))
28 RK3036_PLL_RATE(1188000000, 1, 99, 2, 1, 1, 0),
29 RK3036_PLL_RATE(1104000000, 1, 92, 2, 1, 1, 0),
30 RK3036_PLL_RATE(1008000000, 1, 84, 2, 1, 1, 0),
31 RK3036_PLL_RATE(1000000000, 3, 250, 2, 1, 1, 0),
32 RK3036_PLL_RATE(816000000, 1, 68, 2, 1, 1, 0),
33 RK3036_PLL_RATE(600000000, 1, 100, 4, 1, 1, 0),
34 RK3036_PLL_RATE(594000000, 1, 99, 4, 1, 1, 0),
83 con = readl(&cru->peri_clksel_con[1]); in rv1106_peri_get_clk()
86 rate = 400 * MHz; in rv1106_peri_get_clk()
[all …]
H A Dclk_rk3568.c30 #define DIV_TO_RATE(input_rate, div) ((input_rate) / ((div) + 1))
33 RK3568_CPUCLK_RATE(1416000000, 1, 5),
34 RK3568_CPUCLK_RATE(1296000000, 1, 5),
35 RK3568_CPUCLK_RATE(1200000000, 1, 3),
36 RK3568_CPUCLK_RATE(1104000000, 1, 3),
37 RK3568_CPUCLK_RATE(1008000000, 1, 3),
38 RK3568_CPUCLK_RATE(912000000, 1, 3),
39 RK3568_CPUCLK_RATE(816000000, 1, 3),
40 RK3568_CPUCLK_RATE(600000000, 1, 1),
41 RK3568_CPUCLK_RATE(408000000, 1, 1),
[all …]
/OK3568_Linux_fs/kernel/drivers/media/tuners/
H A Dtuner-types.c65 { 16 * 140.25 /*MHz*/, 0x8e, 0x02, },
66 { 16 * 463.25 /*MHz*/, 0x8e, 0x04, },
81 { 16 * 140.25 /*MHz*/, 0x8e, 0xa0, },
82 { 16 * 463.25 /*MHz*/, 0x8e, 0x90, },
97 { 16 * 157.25 /*MHz*/, 0x8e, 0xa0, },
98 { 16 * 451.25 /*MHz*/, 0x8e, 0x90, },
107 .cb_first_if_lower_freq = 1,
114 { 16 * 168.25 /*MHz*/, 0x8e, 0xa7, },
115 { 16 * 447.25 /*MHz*/, 0x8e, 0x97, },
124 .cb_first_if_lower_freq = 1,
[all …]

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