17 	ret = i2c_read(idt_addr, 0x17, 1, &val, 1);  in check_pll_status()
28 		return -1;  in check_pll_status()
44 	ret = i2c_read(idt_addr, DEVICE_ID_REG, 1, &dev_id, 1);  in set_serdes_refclk()
56 	if (serdes_num != 1 && serdes_num != 2) {  in set_serdes_refclk()
57 		debug("serdes_num should be 1 for SerDes1 and"  in set_serdes_refclk()
59 		return -1;  in set_serdes_refclk()
65 		debug("Only one refclk at 122.88MHz is not supported."  in set_serdes_refclk()
66 			" Please set both refclk1 & refclk2 to 122.88MHz"  in set_serdes_refclk()
67 			" or both not to 122.88MHz.\n");  in set_serdes_refclk()
68 		return -1;  in set_serdes_refclk()
74 		debug("refclk1 should be 100MHZ, 122.88MHz, 125MHz"  in set_serdes_refclk()
75 			" or 156.25MHz.\n");  in set_serdes_refclk()
76 		return -1;  in set_serdes_refclk()
82 		debug("refclk2 should be 100MHZ, 122.88MHz, 125MHz"  in set_serdes_refclk()
83 			" or 156.25MHz.\n");  in set_serdes_refclk()
84 		return -1;  in set_serdes_refclk()
87 	if (feedback != 0 && feedback != 1) {  in set_serdes_refclk()
88 		debug("valid values for feedback are 0(default) or 1.\n");  in set_serdes_refclk()
89 		return -1;  in set_serdes_refclk()
93 	 * Refclk1 = 122.88MHz  Refclk2 = 122.88MHz  in set_serdes_refclk()
100 						idt_conf_122_88[i][1]);  in set_serdes_refclk()
106 					idt_conf_122_88_feedback[i][1]);  in set_serdes_refclk()
114 						idt_conf_not_122_88[i][1]);  in set_serdes_refclk()
118 	 * Refclk1 = 100MHz  Refclk2 = 125MHz  in set_serdes_refclk()
126 	 * Refclk1 = 125MHz  Refclk2 = 125MHz  in set_serdes_refclk()
135 	 * Refclk1 = 125MHz  Refclk2 = 100MHz  in set_serdes_refclk()
143 	 * Refclk1 = 156.25MHz  Refclk2 = 156.25MHz  in set_serdes_refclk()
150 						idt_conf_156_25[i][1]);  in set_serdes_refclk()
154 	 * Refclk1 = 100MHz  Refclk2 = 156.25MHz  in set_serdes_refclk()
161 						idt_conf_100_156_25[i][1]);  in set_serdes_refclk()
165 	 * Refclk1 = 125MHz  Refclk2 = 156.25MHz  in set_serdes_refclk()
172 						idt_conf_125_156_25[i][1]);  in set_serdes_refclk()
176 	 * Refclk1 = 156.25MHz  Refclk2 = 100MHz  in set_serdes_refclk()
183 						idt_conf_156_25_100[i][1]);  in set_serdes_refclk()
187 	 * Refclk1 = 156.25MHz  Refclk2 = 125MHz  in set_serdes_refclk()
194 						idt_conf_156_25_125[i][1]);  in set_serdes_refclk()
197 	/* waiting for maximum of 1 second if PLL doesn'r get locked  in set_serdes_refclk()
203 			return -1;  in set_serdes_refclk()