Searched +full:0 +full:x7000f000 (Results 1 – 9 of 9) sorted by relevance
11 #define NV_PA_SDRAM_BASE 0x0000000012 #define NV_PA_MC_BASE 0x7000F00016 #define TEGRA_USB1_BASE 0xC5000000
10 #define NV_PA_MC_BASE 0x7000F00011 #define NV_PA_SDRAM_BASE 0x80000000 /* 0x80000000 for real T30 */15 #define TEGRA_USB1_BASE 0x7D000000
15 - #iommu-cells: Should be 0. This cell represents the number of cells in an23 reg = <0x7000f000 0x400 /* controller registers */24 0x58000000 0x02000000>; /* GART aperture */27 interrupts = <GIC_SPI 77 0x04>;29 #iommu-cells = <0>;
61 "^emc-timings-[0-9]+$":70 "^timing-[0-9]+$":130 reg = <0x7000f000 0x400>;134 interrupts = <0 77 4>;146 0x0000000a /* MC_EMEM_ARB_CFG */147 0xc0000079 /* MC_EMEM_ARB_OUTSTANDING_REQ */148 0x00000003 /* MC_EMEM_ARB_TIMING_RCD */149 0x00000004 /* MC_EMEM_ARB_TIMING_RP */150 0x00000010 /* MC_EMEM_ARB_TIMING_RC */151 0x0000000b /* MC_EMEM_ARB_TIMING_RAS */[all …]
14 reg = <0x50000000 0x00024000>;24 ranges = <0x54000000 0x54000000 0x04000000>;28 reg = <0x54040000 0x00040000>;37 reg = <0x54080000 0x00040000>;46 reg = <0x540c0000 0x00040000>;55 reg = <0x54100000 0x00040000>;64 reg = <0x54140000 0x00040000>;73 reg = <0x54180000 0x00040000>;81 reg = <0x54200000 0x00040000>;89 nvidia,head = <0>;[all …]
16 reg = <0x00003000 0x00000800 /* PADS registers */17 0x00003800 0x00000200 /* AFI registers */18 0x10000000 0x10000000>; /* configuration space */25 interrupt-map-mask = <0 0 0 0>;26 interrupt-map = <0 0 0 0 &intc GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;28 bus-range = <0x00 0xff>;32 ranges = <0x82000000 0 0x00000000 0x00000000 0 0x00001000 /* port 0 configuration space */33 0x82000000 0 0x00001000 0x00001000 0 0x00001000 /* port 1 configuration space */34 0x82000000 0 0x00004000 0x00004000 0 0x00001000 /* port 2 configuration space */35 0x81000000 0 0 0x02000000 0 0x00010000 /* downstream I/O */[all …]
66 #define SCU_VIIT_ENTRY_ID_MASK (0xC0000000)69 #define SCU_VIIT_ENTRY_FUNCTION_MASK (0x0FF00000)72 #define SCU_VIIT_ENTRY_IPPTMODE_MASK (0x0001F800)75 #define SCU_VIIT_ENTRY_LPVIE_MASK (0x00000F00)78 #define SCU_VIIT_ENTRY_STATUS_MASK (0x000000FF)79 #define SCU_VIIT_ENTRY_STATUS_SHIFT (0)81 #define SCU_VIIT_ENTRY_ID_INVALID (0 << SCU_VIIT_ENTRY_ID_SHIFT)86 #define SCU_VIIT_IPPT_SSP_INITIATOR (0x01 << SCU_VIIT_ENTRY_IPPTMODE_SHIFT)87 #define SCU_VIIT_IPPT_SMP_INITIATOR (0x02 << SCU_VIIT_ENTRY_IPPTMODE_SHIFT)88 #define SCU_VIIT_IPPT_STP_INITIATOR (0x04 << SCU_VIIT_ENTRY_IPPTMODE_SHIFT)[all …]
15 memory@0 {17 reg = <0 0>;22 reg = <0x40000000 0x40000>;25 ranges = <0 0x40000000 0x40000>;28 reg = <0x400 0x3fc00>;35 reg = <0x50000000 0x00024000>;47 ranges = <0x54000000 0x54000000 0x04000000>;51 reg = <0x54040000 0x00040000>;60 reg = <0x54080000 0x00040000>;69 reg = <0x540c0000 0x00040000>;[all …]
17 reg = <0x80000000 0x0>;23 reg = <0x00003000 0x00000800>, /* PADS registers */24 <0x00003800 0x00000200>, /* AFI registers */25 <0x10000000 0x10000000>; /* configuration space */32 interrupt-map-mask = <0 0 0 0>;33 interrupt-map = <0 0 0 0 &intc GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;35 bus-range = <0x00 0xff>;39 ranges = <0x02000000 0 0x00000000 0x00000000 0 0x00001000>, /* port 0 configuration space */40 <0x02000000 0 0x00001000 0x00001000 0 0x00001000>, /* port 1 configuration space */41 <0x02000000 0 0x00004000 0x00004000 0 0x00001000>, /* port 2 configuration space */[all …]