1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Copyright (c) 2010-2012, NVIDIA CORPORATION. All rights reserved. 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun #ifndef _TEGRA30_H_ 8*4882a593Smuzhiyun #define _TEGRA30_H_ 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun #define NV_PA_MC_BASE 0x7000F000 11*4882a593Smuzhiyun #define NV_PA_SDRAM_BASE 0x80000000 /* 0x80000000 for real T30 */ 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun #include <asm/arch-tegra/tegra.h> 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun #define TEGRA_USB1_BASE 0x7D000000 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun #define BCT_ODMDATA_OFFSET 6116 /* 12 bytes from end of BCT */ 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun #define MAX_NUM_CPU 4 20*4882a593Smuzhiyun 21*4882a593Smuzhiyun #endif /* TEGRA30_H */ 22