1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * (C) Copyright 2010,2011 3*4882a593Smuzhiyun * NVIDIA Corporation <www.nvidia.com> 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 6*4882a593Smuzhiyun */ 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun #ifndef _TEGRA20_H_ 9*4882a593Smuzhiyun #define _TEGRA20_H_ 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun #define NV_PA_SDRAM_BASE 0x00000000 12*4882a593Smuzhiyun #define NV_PA_MC_BASE 0x7000F000 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun #include <asm/arch-tegra/tegra.h> 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun #define TEGRA_USB1_BASE 0xC5000000 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun #define BCT_ODMDATA_OFFSET 4068 /* 12 bytes from end of BCT */ 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun #define MAX_NUM_CPU 2 21*4882a593Smuzhiyun 22*4882a593Smuzhiyun #endif /* TEGRA20_H */ 23