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/OK3568_Linux_fs/kernel/include/dt-bindings/clock/
H A Dam4.h8 #define AM4_CLKCTRL_OFFSET 0x20
14 #define AM4_ADC_TSC_CLKCTRL AM4_CLKCTRL_INDEX(0x120)
15 #define AM4_L4_WKUP_CLKCTRL AM4_CLKCTRL_INDEX(0x220)
16 #define AM4_WKUP_M3_CLKCTRL AM4_CLKCTRL_INDEX(0x228)
17 #define AM4_COUNTER_32K_CLKCTRL AM4_CLKCTRL_INDEX(0x230)
18 #define AM4_TIMER1_CLKCTRL AM4_CLKCTRL_INDEX(0x328)
19 #define AM4_WD_TIMER2_CLKCTRL AM4_CLKCTRL_INDEX(0x338)
20 #define AM4_I2C1_CLKCTRL AM4_CLKCTRL_INDEX(0x340)
21 #define AM4_UART1_CLKCTRL AM4_CLKCTRL_INDEX(0x348)
22 #define AM4_SMARTREFLEX0_CLKCTRL AM4_CLKCTRL_INDEX(0x350)
[all …]
/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/pinctrl/
H A Dfsl,imx8mn-pinctrl.yaml72 reg = <0x30330000 0x10000>;
76 <0x23C 0x4A4 0x4FC 0x0 0x0 0x140>,
77 <0x240 0x4A8 0x000 0x0 0x0 0x140>;
H A Dfsl,imx8mm-pinctrl.yaml72 reg = <0x30330000 0x10000>;
76 <0x23C 0x4A4 0x4FC 0x0 0x0 0x140>,
77 <0x240 0x4A8 0x000 0x0 0x0 0x140>;
/OK3568_Linux_fs/kernel/arch/arm64/boot/dts/freescale/
H A Dimx8mq-pinfunc.h15 #define MX8MQ_IOMUXC_PMIC_STBY_REQ_CCMSRCGPCMIX_PMIC_STBY_REQ 0x014 0x27C 0x000 0x0 0…
16 #define MX8MQ_IOMUXC_PMIC_ON_REQ_SNVSMIX_PMIC_ON_REQ 0x018 0x280 0x000 0x0 0…
17 #define MX8MQ_IOMUXC_ONOFF_SNVSMIX_ONOFF 0x01C 0x284 0x000 0x0 0…
18 #define MX8MQ_IOMUXC_POR_B_SNVSMIX_POR_B 0x020 0x288 0x000 0x0 0…
19 #define MX8MQ_IOMUXC_RTC_RESET_B_SNVSMIX_RTC_RESET_B 0x024 0x28C 0x000 0x0 0…
20 #define MX8MQ_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x028 0x290 0x000 0x0 0…
21 #define MX8MQ_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_ENET_PHY_REF_CLK_ROOT 0x028 0x290 0x4C0 0x1 0…
22 #define MX8MQ_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x028 0x290 0x000 0x5 0…
23 #define MX8MQ_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_EXT_CLK1 0x028 0x290 0x000 0x6 0…
24 #define MX8MQ_IOMUXC_GPIO1_IO00_SJC_FAIL 0x028 0x290 0x000 0x7 0…
[all …]
H A Dimx8mn-pinfunc.h14 …ne MX8MN_IOMUXC_BOOT_MODE2_CCMSRCGPCMIX_BOOT_MODE2 0x020 0x25C 0x000 0x0 0x0
15 …ne MX8MN_IOMUXC_BOOT_MODE2_I2C1_SCL 0x020 0x25C 0x55C 0x1 0x3
16 …ne MX8MN_IOMUXC_BOOT_MODE3_CCMSRCGPCMIX_BOOT_MODE3 0x024 0x260 0x000 0x0 0x0
17 …ne MX8MN_IOMUXC_BOOT_MODE3_I2C1_SDA 0x024 0x260 0x56C 0x1 0x3
18 …ne MX8MN_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x028 0x290 0x000 0x0 0x0
19 …ne MX8MN_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_ENET_PHY_REF_CLK_ROOT 0x028 0x290 0x000 0x1 0x0
20 …ne MX8MN_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x028 0x290 0x000 0x5 0x0
21 …ne MX8MN_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_EXT_CLK1 0x028 0x290 0x000 0x6 0x0
22 …ne MX8MN_IOMUXC_GPIO1_IO01_GPIO1_IO1 0x02C 0x294 0x000 0x0 0x0
23 …ne MX8MN_IOMUXC_GPIO1_IO01_PWM1_OUT 0x02C 0x294 0x000 0x1 0x0
[all …]
H A Dimx8mm-pinfunc.h14 #define MX8MM_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x028 0x290 0x000 0x0 0…
15 #define MX8MM_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_ENET_PHY_REF_CLK_ROOT 0x028 0x290 0x4C0 0x1 0…
16 #define MX8MM_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x028 0x290 0x000 0x5 0…
17 #define MX8MM_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_EXT_CLK1 0x028 0x290 0x000 0x6 0…
18 #define MX8MM_IOMUXC_GPIO1_IO00_SJC_FAIL 0x028 0x290 0x000 0x7 0…
19 #define MX8MM_IOMUXC_GPIO1_IO01_GPIO1_IO1 0x02C 0x294 0x000 0x0 0…
20 #define MX8MM_IOMUXC_GPIO1_IO01_PWM1_OUT 0x02C 0x294 0x000 0x1 0…
21 #define MX8MM_IOMUXC_GPIO1_IO01_ANAMIX_REF_CLK_24M 0x02C 0x294 0x4BC 0x5 0…
22 #define MX8MM_IOMUXC_GPIO1_IO01_CCMSRCGPCMIX_EXT_CLK2 0x02C 0x294 0x000 0x6 0…
23 #define MX8MM_IOMUXC_GPIO1_IO01_SJC_ACTIVE 0x02C 0x294 0x000 0x7 0…
[all …]
H A Dimx8mp-pinfunc.h13 #define MX8MP_IOMUXC_GPIO1_IO00__GPIO1_IO00 0x014 0x274 0x000 0x0 0x0
14 #define MX8MP_IOMUXC_GPIO1_IO00__CCM_ENET_PHY_REF_CLK_ROOT 0x014 0x274 0x000 0x1 0x0
15 #define MX8MP_IOMUXC_GPIO1_IO00__ISP_FL_TRIG_0 0x014 0x274 0x5D4 0x3 0x0
16 #define MX8MP_IOMUXC_GPIO1_IO00__CCM_EXT_CLK1 0x014 0x274 0x000 0x6 0x0
17 #define MX8MP_IOMUXC_GPIO1_IO01__GPIO1_IO01 0x018 0x278 0x000 0x0 0x0
18 #define MX8MP_IOMUXC_GPIO1_IO01__PWM1_OUT 0x018 0x278 0x000 0x1 0x0
19 #define MX8MP_IOMUXC_GPIO1_IO01__ISP_SHUTTER_TRIG_0 0x018 0x278 0x5DC 0x3 0x0
20 #define MX8MP_IOMUXC_GPIO1_IO01__CCM_EXT_CLK2 0x018 0x278 0x000 0x6 0x0
21 #define MX8MP_IOMUXC_GPIO1_IO02__GPIO1_IO02 0x01C 0x27C 0x000 0x0 0x0
22 #define MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B 0x01C 0x27C 0x000 0x1 0x0
[all …]
/OK3568_Linux_fs/kernel/drivers/misc/habanalabs/include/goya/asic_reg/
H A Dpci_nrtr_regs.h22 #define mmPCI_NRTR_HBW_MAX_CRED 0x100
24 #define mmPCI_NRTR_LBW_MAX_CRED 0x120
26 #define mmPCI_NRTR_DBG_E_ARB 0x300
28 #define mmPCI_NRTR_DBG_W_ARB 0x304
30 #define mmPCI_NRTR_DBG_N_ARB 0x308
32 #define mmPCI_NRTR_DBG_S_ARB 0x30C
34 #define mmPCI_NRTR_DBG_L_ARB 0x310
36 #define mmPCI_NRTR_DBG_E_ARB_MAX 0x320
38 #define mmPCI_NRTR_DBG_W_ARB_MAX 0x324
40 #define mmPCI_NRTR_DBG_N_ARB_MAX 0x328
[all …]
/OK3568_Linux_fs/buildroot/package/iftop/
H A D0002-Rename-pcap_filter-to-iftop_pcap_filter.patch10 …t-1/host/opt/ext-toolchain/bin/../lib/gcc/riscv64-buildroot-linux-musl/10.2.0/../../../../riscv64-…
11 bpf_filter.c:(.text+0x4a8): multiple definition of `pcap_filter'; iftop.o:iftop.c:(.bss+0x1a8): fir…
38 - if (pcap_compile(pd, &pcap_filter, x, 1, 0) == -1) {
39 + if (pcap_compile(pd, &iftop_pcap_filter, x, 1, 0) == -1) {
/OK3568_Linux_fs/u-boot/arch/arm/dts/
H A Dimx6sl-pinfunc.h17 #define MX6SL_PAD_AUD_MCLK__AUDIO_CLK_OUT 0x04c 0x2a4 0x000 0x0 0x0
18 #define MX6SL_PAD_AUD_MCLK__PWM4_OUT 0x04c 0x2a4 0x000 0x1 0x0
19 #define MX6SL_PAD_AUD_MCLK__ECSPI3_RDY 0x04c 0x2a4 0x6b4 0x2 0x0
20 #define MX6SL_PAD_AUD_MCLK__FEC_MDC 0x04c 0x2a4 0x000 0x3 0x0
21 #define MX6SL_PAD_AUD_MCLK__WDOG2_RESET_B_DEB 0x04c 0x2a4 0x000 0x4 0x0
22 #define MX6SL_PAD_AUD_MCLK__GPIO1_IO06 0x04c 0x2a4 0x000 0x5 0x0
23 #define MX6SL_PAD_AUD_MCLK__SPDIF_EXT_CLK 0x04c 0x2a4 0x7f4 0x6 0x0
24 #define MX6SL_PAD_AUD_RXC__AUD3_RXC 0x050 0x2a8 0x000 0x0 0x0
25 #define MX6SL_PAD_AUD_RXC__I2C1_SDA 0x050 0x2a8 0x720 0x1 0x0
26 #define MX6SL_PAD_AUD_RXC__UART3_TX_DATA 0x050 0x2a8 0x000 0x2 0x0
[all …]
H A Dimx53-pinfunc.h17 #define MX53_PAD_GPIO_19__KPP_COL_5 0x020 0x348 0x840 0x0 0x0
18 #define MX53_PAD_GPIO_19__GPIO4_5 0x020 0x348 0x000 0x1 0x0
19 #define MX53_PAD_GPIO_19__CCM_CLKO 0x020 0x348 0x000 0x2 0x0
20 #define MX53_PAD_GPIO_19__SPDIF_OUT1 0x020 0x348 0x000 0x3 0x0
21 #define MX53_PAD_GPIO_19__RTC_CE_RTC_EXT_TRIG2 0x020 0x348 0x000 0x4 0x0
22 #define MX53_PAD_GPIO_19__ECSPI1_RDY 0x020 0x348 0x000 0x5 0x0
23 #define MX53_PAD_GPIO_19__FEC_TDATA_3 0x020 0x348 0x000 0x6 0x0
24 #define MX53_PAD_GPIO_19__SRC_INT_BOOT 0x020 0x348 0x000 0x7 0x0
25 #define MX53_PAD_KEY_COL0__KPP_COL_0 0x024 0x34c 0x000 0x0 0x0
26 #define MX53_PAD_KEY_COL0__GPIO4_6 0x024 0x34c 0x000 0x1 0x0
[all …]
H A Dimx6q-pinfunc.h17 #define MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x04c 0x360 0x000 0x0 0x0
18 #define MX6QDL_PAD_SD2_DAT1__ECSPI5_SS0 0x04c 0x360 0x834 0x1 0x0
19 #define MX6QDL_PAD_SD2_DAT1__EIM_CS2_B 0x04c 0x360 0x000 0x2 0x0
20 #define MX6QDL_PAD_SD2_DAT1__AUD4_TXFS 0x04c 0x360 0x7c8 0x3 0x0
21 #define MX6QDL_PAD_SD2_DAT1__KEY_COL7 0x04c 0x360 0x8f0 0x4 0x0
22 #define MX6QDL_PAD_SD2_DAT1__GPIO1_IO14 0x04c 0x360 0x000 0x5 0x0
23 #define MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x050 0x364 0x000 0x0 0x0
24 #define MX6QDL_PAD_SD2_DAT2__ECSPI5_SS1 0x050 0x364 0x838 0x1 0x0
25 #define MX6QDL_PAD_SD2_DAT2__EIM_CS3_B 0x050 0x364 0x000 0x2 0x0
26 #define MX6QDL_PAD_SD2_DAT2__AUD4_TXD 0x050 0x364 0x7b8 0x3 0x0
[all …]
/OK3568_Linux_fs/kernel/arch/arm/boot/dts/
H A Dimx6sl-pinfunc.h13 #define MX6SL_PAD_AUD_MCLK__AUDIO_CLK_OUT 0x04c 0x2a4 0x000 0x0 0x0
14 #define MX6SL_PAD_AUD_MCLK__PWM4_OUT 0x04c 0x2a4 0x000 0x1 0x0
15 #define MX6SL_PAD_AUD_MCLK__ECSPI3_RDY 0x04c 0x2a4 0x6b4 0x2 0x0
16 #define MX6SL_PAD_AUD_MCLK__FEC_MDC 0x04c 0x2a4 0x000 0x3 0x0
17 #define MX6SL_PAD_AUD_MCLK__WDOG2_RESET_B_DEB 0x04c 0x2a4 0x000 0x4 0x0
18 #define MX6SL_PAD_AUD_MCLK__GPIO1_IO06 0x04c 0x2a4 0x000 0x5 0x0
19 #define MX6SL_PAD_AUD_MCLK__SPDIF_EXT_CLK 0x04c 0x2a4 0x7f4 0x6 0x0
20 #define MX6SL_PAD_AUD_RXC__AUD3_RXC 0x050 0x2a8 0x000 0x0 0x0
21 #define MX6SL_PAD_AUD_RXC__I2C1_SDA 0x050 0x2a8 0x720 0x1 0x0
22 #define MX6SL_PAD_AUD_RXC__UART3_TX_DATA 0x050 0x2a8 0x000 0x2 0x0
[all …]
H A Dimx53-pinfunc.h13 #define MX53_PAD_GPIO_19__KPP_COL_5 0x020 0x348 0x840 0x0 0x0
14 #define MX53_PAD_GPIO_19__GPIO4_5 0x020 0x348 0x000 0x1 0x0
15 #define MX53_PAD_GPIO_19__CCM_CLKO 0x020 0x348 0x000 0x2 0x0
16 #define MX53_PAD_GPIO_19__SPDIF_OUT1 0x020 0x348 0x000 0x3 0x0
17 #define MX53_PAD_GPIO_19__RTC_CE_RTC_EXT_TRIG2 0x020 0x348 0x000 0x4 0x0
18 #define MX53_PAD_GPIO_19__ECSPI1_RDY 0x020 0x348 0x000 0x5 0x0
19 #define MX53_PAD_GPIO_19__FEC_TDATA_3 0x020 0x348 0x000 0x6 0x0
20 #define MX53_PAD_GPIO_19__SRC_INT_BOOT 0x020 0x348 0x000 0x7 0x0
21 #define MX53_PAD_KEY_COL0__KPP_COL_0 0x024 0x34c 0x000 0x0 0x0
22 #define MX53_PAD_KEY_COL0__GPIO4_6 0x024 0x34c 0x000 0x1 0x0
[all …]
H A Dimx6q-pinfunc.h13 #define MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x04c 0x360 0x000 0x0 0x0
14 #define MX6QDL_PAD_SD2_DAT1__ECSPI5_SS0 0x04c 0x360 0x834 0x1 0x0
15 #define MX6QDL_PAD_SD2_DAT1__EIM_CS2_B 0x04c 0x360 0x000 0x2 0x0
16 #define MX6QDL_PAD_SD2_DAT1__AUD4_TXFS 0x04c 0x360 0x7c8 0x3 0x0
17 #define MX6QDL_PAD_SD2_DAT1__KEY_COL7 0x04c 0x360 0x8f0 0x4 0x0
18 #define MX6QDL_PAD_SD2_DAT1__GPIO1_IO14 0x04c 0x360 0x000 0x5 0x0
19 #define MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x050 0x364 0x000 0x0 0x0
20 #define MX6QDL_PAD_SD2_DAT2__ECSPI5_SS1 0x050 0x364 0x838 0x1 0x0
21 #define MX6QDL_PAD_SD2_DAT2__EIM_CS3_B 0x050 0x364 0x000 0x2 0x0
22 #define MX6QDL_PAD_SD2_DAT2__AUD4_TXD 0x050 0x364 0x7b8 0x3 0x0
[all …]
/OK3568_Linux_fs/kernel/drivers/ntb/hw/amd/
H A Dntb_hw_amd.h56 #define NTB_LNK_STA_SPEED_MASK 0x000F0000
57 #define NTB_LNK_STA_WIDTH_MASK 0x03F00000
97 AMD_CNTL_OFFSET = 0x200,
106 AMD_STA_OFFSET = 0x204,
107 AMD_PGSLV_OFFSET = 0x208,
108 AMD_SPAD_MUX_OFFSET = 0x20C,
109 AMD_SPAD_OFFSET = 0x210,
110 AMD_RSMU_HCID = 0x250,
111 AMD_RSMU_SIID = 0x254,
112 AMD_PSION_OFFSET = 0x300,
[all …]
/OK3568_Linux_fs/u-boot/arch/arm/include/asm/arch-rockchip/
H A Dgrf_rk3308.h63 unsigned int reserved15[(0x100 - 0xec) / 4 - 1];
121 unsigned int reserved24[(0x300 - 0x1EC) / 4 - 1];
133 unsigned int reserved25[(0x380 - 0x328) / 4 - 1];
135 unsigned int reserved26[(0x400 - 0x380) / 4 - 1];
139 unsigned int reserved27[(0x420 - 0x408) / 4 - 1];
142 unsigned int reserved28[(0x440 - 0x424) / 4 - 1];
147 unsigned int reserved29[(0x460 - 0x44C) / 4 - 1];
150 unsigned int reserved30[(0x480 - 0x464) / 4 - 1];
155 unsigned int reserved31[(0x4a0 - 0x48C) / 4 - 1];
159 unsigned int reserved32[(0x500 - 0x4A8) / 4 - 1];
[all …]
/OK3568_Linux_fs/kernel/drivers/clk/tegra/
H A Dclk-tegra-audio.c17 #define AUDIO_SYNC_CLK_I2S0 0x4a0
18 #define AUDIO_SYNC_CLK_I2S1 0x4a4
19 #define AUDIO_SYNC_CLK_I2S2 0x4a8
20 #define AUDIO_SYNC_CLK_I2S3 0x4ac
21 #define AUDIO_SYNC_CLK_I2S4 0x4b0
22 #define AUDIO_SYNC_CLK_SPDIF 0x4b4
23 #define AUDIO_SYNC_CLK_DMIC1 0x560
24 #define AUDIO_SYNC_CLK_DMIC2 0x564
25 #define AUDIO_SYNC_CLK_DMIC3 0x6b8
27 #define AUDIO_SYNC_DOUBLER 0x49c
[all …]
/OK3568_Linux_fs/kernel/drivers/staging/mt7621-pci-phy/
H A Dpci-mt7621-phy.c19 #define RG_PE1_PIPE_REG 0x02c
23 #define RG_P0_TO_P1_WIDTH 0x100
24 #define RG_PE1_H_LCDDS_REG 0x49c
25 #define RG_PE1_H_LCDDS_PCW GENMASK(30, 0)
26 #define RG_PE1_H_LCDDS_PCW_VAL(x) ((0x7fffffff & (x)) << 0)
28 #define RG_PE1_FRC_H_XTAL_REG 0x400
31 #define RG_PE1_H_XTAL_TYPE_VAL(x) ((0x3 & (x)) << 9)
33 #define RG_PE1_FRC_PHY_REG 0x000
37 #define RG_PE1_H_PLL_REG 0x490
39 #define RG_PE1_H_PLL_BC_VAL(x) ((0x3 & (x)) << 22)
[all …]
/OK3568_Linux_fs/external/rkwifibt/drivers/rtl8723ds/hal/phydm/
H A Dphydm_rainfo.h50 #define FIRST_MACID 0
59 RADBG_PCR_TH_OFFSET = 0,
70 RADBG_DEBUG_MONITOR1 = 0xc,
71 RADBG_DEBUG_MONITOR2 = 0xd,
72 RADBG_DEBUG_MONITOR3 = 0xe,
73 RADBG_DEBUG_MONITOR4 = 0xf,
74 RADBG_DEBUG_MONITOR5 = 0x10,
79 PHYDM_WIRELESS_MODE_UNKNOWN = 0x00,
80 PHYDM_WIRELESS_MODE_A = 0x01,
81 PHYDM_WIRELESS_MODE_B = 0x02,
[all …]
/OK3568_Linux_fs/external/rkwifibt/drivers/rtl8189fs/hal/phydm/
H A Dphydm_rainfo.h50 #define FIRST_MACID 0
59 RADBG_PCR_TH_OFFSET = 0,
70 RADBG_DEBUG_MONITOR1 = 0xc,
71 RADBG_DEBUG_MONITOR2 = 0xd,
72 RADBG_DEBUG_MONITOR3 = 0xe,
73 RADBG_DEBUG_MONITOR4 = 0xf,
74 RADBG_DEBUG_MONITOR5 = 0x10,
79 PHYDM_WIRELESS_MODE_UNKNOWN = 0x00,
80 PHYDM_WIRELESS_MODE_A = 0x01,
81 PHYDM_WIRELESS_MODE_B = 0x02,
[all …]
/OK3568_Linux_fs/external/rkwifibt/drivers/rtl8821cs/hal/phydm/
H A Dphydm_rainfo.h50 #define FIRST_MACID 0
59 RADBG_PCR_TH_OFFSET = 0,
70 RADBG_DEBUG_MONITOR1 = 0xc,
71 RADBG_DEBUG_MONITOR2 = 0xd,
72 RADBG_DEBUG_MONITOR3 = 0xe,
73 RADBG_DEBUG_MONITOR4 = 0xf,
74 RADBG_DEBUG_MONITOR5 = 0x10,
79 PHYDM_WIRELESS_MODE_UNKNOWN = 0x00,
80 PHYDM_WIRELESS_MODE_A = 0x01,
81 PHYDM_WIRELESS_MODE_B = 0x02,
[all …]
/OK3568_Linux_fs/kernel/drivers/net/wireless/rockchip_wlan/rtl8723cs/hal/phydm/
H A Dphydm_rainfo.h50 #define FIRST_MACID 0
59 RADBG_PCR_TH_OFFSET = 0,
70 RADBG_DEBUG_MONITOR1 = 0xc,
71 RADBG_DEBUG_MONITOR2 = 0xd,
72 RADBG_DEBUG_MONITOR3 = 0xe,
73 RADBG_DEBUG_MONITOR4 = 0xf,
74 RADBG_DEBUG_MONITOR5 = 0x10,
79 PHYDM_WIRELESS_MODE_UNKNOWN = 0x00,
80 PHYDM_WIRELESS_MODE_A = 0x01,
81 PHYDM_WIRELESS_MODE_B = 0x02,
[all …]
/OK3568_Linux_fs/kernel/drivers/net/wireless/rockchip_wlan/rtl8821cs/hal/phydm/
H A Dphydm_rainfo.h51 #define FIRST_MACID 0
60 RADBG_PCR_TH_OFFSET = 0,
71 RADBG_DEBUG_MONITOR1 = 0xc,
72 RADBG_DEBUG_MONITOR2 = 0xd,
73 RADBG_DEBUG_MONITOR3 = 0xe,
74 RADBG_DEBUG_MONITOR4 = 0xf,
75 RADBG_DEBUG_MONITOR5 = 0x10,
80 PHYDM_WIRELESS_MODE_UNKNOWN = 0x00,
81 PHYDM_WIRELESS_MODE_A = 0x01,
82 PHYDM_WIRELESS_MODE_B = 0x02,
[all …]
/OK3568_Linux_fs/external/rkwifibt/drivers/rtl8822cs/hal/phydm/
H A Dphydm_rainfo.h50 #define FIRST_MACID 0
59 RADBG_PCR_TH_OFFSET = 0,
70 RADBG_DEBUG_MONITOR1 = 0xc,
71 RADBG_DEBUG_MONITOR2 = 0xd,
72 RADBG_DEBUG_MONITOR3 = 0xe,
73 RADBG_DEBUG_MONITOR4 = 0xf,
74 RADBG_DEBUG_MONITOR5 = 0x10,
79 PHYDM_WIRELESS_MODE_UNKNOWN = 0x00,
80 PHYDM_WIRELESS_MODE_A = 0x01,
81 PHYDM_WIRELESS_MODE_B = 0x02,
[all …]

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