1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Copyright 2017 Texas Instruments, Inc. 4*4882a593Smuzhiyun */ 5*4882a593Smuzhiyun #ifndef __DT_BINDINGS_CLK_AM4_H 6*4882a593Smuzhiyun #define __DT_BINDINGS_CLK_AM4_H 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun #define AM4_CLKCTRL_OFFSET 0x20 9*4882a593Smuzhiyun #define AM4_CLKCTRL_INDEX(offset) ((offset) - AM4_CLKCTRL_OFFSET) 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun /* XXX: Compatibility part begin, remove this once compatibility support is no longer needed */ 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun /* l4_wkup clocks */ 14*4882a593Smuzhiyun #define AM4_ADC_TSC_CLKCTRL AM4_CLKCTRL_INDEX(0x120) 15*4882a593Smuzhiyun #define AM4_L4_WKUP_CLKCTRL AM4_CLKCTRL_INDEX(0x220) 16*4882a593Smuzhiyun #define AM4_WKUP_M3_CLKCTRL AM4_CLKCTRL_INDEX(0x228) 17*4882a593Smuzhiyun #define AM4_COUNTER_32K_CLKCTRL AM4_CLKCTRL_INDEX(0x230) 18*4882a593Smuzhiyun #define AM4_TIMER1_CLKCTRL AM4_CLKCTRL_INDEX(0x328) 19*4882a593Smuzhiyun #define AM4_WD_TIMER2_CLKCTRL AM4_CLKCTRL_INDEX(0x338) 20*4882a593Smuzhiyun #define AM4_I2C1_CLKCTRL AM4_CLKCTRL_INDEX(0x340) 21*4882a593Smuzhiyun #define AM4_UART1_CLKCTRL AM4_CLKCTRL_INDEX(0x348) 22*4882a593Smuzhiyun #define AM4_SMARTREFLEX0_CLKCTRL AM4_CLKCTRL_INDEX(0x350) 23*4882a593Smuzhiyun #define AM4_SMARTREFLEX1_CLKCTRL AM4_CLKCTRL_INDEX(0x358) 24*4882a593Smuzhiyun #define AM4_CONTROL_CLKCTRL AM4_CLKCTRL_INDEX(0x360) 25*4882a593Smuzhiyun #define AM4_GPIO1_CLKCTRL AM4_CLKCTRL_INDEX(0x368) 26*4882a593Smuzhiyun 27*4882a593Smuzhiyun /* mpu clocks */ 28*4882a593Smuzhiyun #define AM4_MPU_CLKCTRL AM4_CLKCTRL_INDEX(0x20) 29*4882a593Smuzhiyun 30*4882a593Smuzhiyun /* gfx_l3 clocks */ 31*4882a593Smuzhiyun #define AM4_GFX_CLKCTRL AM4_CLKCTRL_INDEX(0x20) 32*4882a593Smuzhiyun 33*4882a593Smuzhiyun /* l4_rtc clocks */ 34*4882a593Smuzhiyun #define AM4_RTC_CLKCTRL AM4_CLKCTRL_INDEX(0x20) 35*4882a593Smuzhiyun 36*4882a593Smuzhiyun /* l4_per clocks */ 37*4882a593Smuzhiyun #define AM4_L3_MAIN_CLKCTRL AM4_CLKCTRL_INDEX(0x20) 38*4882a593Smuzhiyun #define AM4_AES_CLKCTRL AM4_CLKCTRL_INDEX(0x28) 39*4882a593Smuzhiyun #define AM4_DES_CLKCTRL AM4_CLKCTRL_INDEX(0x30) 40*4882a593Smuzhiyun #define AM4_L3_INSTR_CLKCTRL AM4_CLKCTRL_INDEX(0x40) 41*4882a593Smuzhiyun #define AM4_OCMCRAM_CLKCTRL AM4_CLKCTRL_INDEX(0x50) 42*4882a593Smuzhiyun #define AM4_SHAM_CLKCTRL AM4_CLKCTRL_INDEX(0x58) 43*4882a593Smuzhiyun #define AM4_VPFE0_CLKCTRL AM4_CLKCTRL_INDEX(0x68) 44*4882a593Smuzhiyun #define AM4_VPFE1_CLKCTRL AM4_CLKCTRL_INDEX(0x70) 45*4882a593Smuzhiyun #define AM4_TPCC_CLKCTRL AM4_CLKCTRL_INDEX(0x78) 46*4882a593Smuzhiyun #define AM4_TPTC0_CLKCTRL AM4_CLKCTRL_INDEX(0x80) 47*4882a593Smuzhiyun #define AM4_TPTC1_CLKCTRL AM4_CLKCTRL_INDEX(0x88) 48*4882a593Smuzhiyun #define AM4_TPTC2_CLKCTRL AM4_CLKCTRL_INDEX(0x90) 49*4882a593Smuzhiyun #define AM4_L4_HS_CLKCTRL AM4_CLKCTRL_INDEX(0xa0) 50*4882a593Smuzhiyun #define AM4_GPMC_CLKCTRL AM4_CLKCTRL_INDEX(0x220) 51*4882a593Smuzhiyun #define AM4_MCASP0_CLKCTRL AM4_CLKCTRL_INDEX(0x238) 52*4882a593Smuzhiyun #define AM4_MCASP1_CLKCTRL AM4_CLKCTRL_INDEX(0x240) 53*4882a593Smuzhiyun #define AM4_MMC3_CLKCTRL AM4_CLKCTRL_INDEX(0x248) 54*4882a593Smuzhiyun #define AM4_QSPI_CLKCTRL AM4_CLKCTRL_INDEX(0x258) 55*4882a593Smuzhiyun #define AM4_USB_OTG_SS0_CLKCTRL AM4_CLKCTRL_INDEX(0x260) 56*4882a593Smuzhiyun #define AM4_USB_OTG_SS1_CLKCTRL AM4_CLKCTRL_INDEX(0x268) 57*4882a593Smuzhiyun #define AM4_PRUSS_CLKCTRL AM4_CLKCTRL_INDEX(0x320) 58*4882a593Smuzhiyun #define AM4_L4_LS_CLKCTRL AM4_CLKCTRL_INDEX(0x420) 59*4882a593Smuzhiyun #define AM4_D_CAN0_CLKCTRL AM4_CLKCTRL_INDEX(0x428) 60*4882a593Smuzhiyun #define AM4_D_CAN1_CLKCTRL AM4_CLKCTRL_INDEX(0x430) 61*4882a593Smuzhiyun #define AM4_EPWMSS0_CLKCTRL AM4_CLKCTRL_INDEX(0x438) 62*4882a593Smuzhiyun #define AM4_EPWMSS1_CLKCTRL AM4_CLKCTRL_INDEX(0x440) 63*4882a593Smuzhiyun #define AM4_EPWMSS2_CLKCTRL AM4_CLKCTRL_INDEX(0x448) 64*4882a593Smuzhiyun #define AM4_EPWMSS3_CLKCTRL AM4_CLKCTRL_INDEX(0x450) 65*4882a593Smuzhiyun #define AM4_EPWMSS4_CLKCTRL AM4_CLKCTRL_INDEX(0x458) 66*4882a593Smuzhiyun #define AM4_EPWMSS5_CLKCTRL AM4_CLKCTRL_INDEX(0x460) 67*4882a593Smuzhiyun #define AM4_ELM_CLKCTRL AM4_CLKCTRL_INDEX(0x468) 68*4882a593Smuzhiyun #define AM4_GPIO2_CLKCTRL AM4_CLKCTRL_INDEX(0x478) 69*4882a593Smuzhiyun #define AM4_GPIO3_CLKCTRL AM4_CLKCTRL_INDEX(0x480) 70*4882a593Smuzhiyun #define AM4_GPIO4_CLKCTRL AM4_CLKCTRL_INDEX(0x488) 71*4882a593Smuzhiyun #define AM4_GPIO5_CLKCTRL AM4_CLKCTRL_INDEX(0x490) 72*4882a593Smuzhiyun #define AM4_GPIO6_CLKCTRL AM4_CLKCTRL_INDEX(0x498) 73*4882a593Smuzhiyun #define AM4_HDQ1W_CLKCTRL AM4_CLKCTRL_INDEX(0x4a0) 74*4882a593Smuzhiyun #define AM4_I2C2_CLKCTRL AM4_CLKCTRL_INDEX(0x4a8) 75*4882a593Smuzhiyun #define AM4_I2C3_CLKCTRL AM4_CLKCTRL_INDEX(0x4b0) 76*4882a593Smuzhiyun #define AM4_MAILBOX_CLKCTRL AM4_CLKCTRL_INDEX(0x4b8) 77*4882a593Smuzhiyun #define AM4_MMC1_CLKCTRL AM4_CLKCTRL_INDEX(0x4c0) 78*4882a593Smuzhiyun #define AM4_MMC2_CLKCTRL AM4_CLKCTRL_INDEX(0x4c8) 79*4882a593Smuzhiyun #define AM4_RNG_CLKCTRL AM4_CLKCTRL_INDEX(0x4e0) 80*4882a593Smuzhiyun #define AM4_SPI0_CLKCTRL AM4_CLKCTRL_INDEX(0x500) 81*4882a593Smuzhiyun #define AM4_SPI1_CLKCTRL AM4_CLKCTRL_INDEX(0x508) 82*4882a593Smuzhiyun #define AM4_SPI2_CLKCTRL AM4_CLKCTRL_INDEX(0x510) 83*4882a593Smuzhiyun #define AM4_SPI3_CLKCTRL AM4_CLKCTRL_INDEX(0x518) 84*4882a593Smuzhiyun #define AM4_SPI4_CLKCTRL AM4_CLKCTRL_INDEX(0x520) 85*4882a593Smuzhiyun #define AM4_SPINLOCK_CLKCTRL AM4_CLKCTRL_INDEX(0x528) 86*4882a593Smuzhiyun #define AM4_TIMER2_CLKCTRL AM4_CLKCTRL_INDEX(0x530) 87*4882a593Smuzhiyun #define AM4_TIMER3_CLKCTRL AM4_CLKCTRL_INDEX(0x538) 88*4882a593Smuzhiyun #define AM4_TIMER4_CLKCTRL AM4_CLKCTRL_INDEX(0x540) 89*4882a593Smuzhiyun #define AM4_TIMER5_CLKCTRL AM4_CLKCTRL_INDEX(0x548) 90*4882a593Smuzhiyun #define AM4_TIMER6_CLKCTRL AM4_CLKCTRL_INDEX(0x550) 91*4882a593Smuzhiyun #define AM4_TIMER7_CLKCTRL AM4_CLKCTRL_INDEX(0x558) 92*4882a593Smuzhiyun #define AM4_TIMER8_CLKCTRL AM4_CLKCTRL_INDEX(0x560) 93*4882a593Smuzhiyun #define AM4_TIMER9_CLKCTRL AM4_CLKCTRL_INDEX(0x568) 94*4882a593Smuzhiyun #define AM4_TIMER10_CLKCTRL AM4_CLKCTRL_INDEX(0x570) 95*4882a593Smuzhiyun #define AM4_TIMER11_CLKCTRL AM4_CLKCTRL_INDEX(0x578) 96*4882a593Smuzhiyun #define AM4_UART2_CLKCTRL AM4_CLKCTRL_INDEX(0x580) 97*4882a593Smuzhiyun #define AM4_UART3_CLKCTRL AM4_CLKCTRL_INDEX(0x588) 98*4882a593Smuzhiyun #define AM4_UART4_CLKCTRL AM4_CLKCTRL_INDEX(0x590) 99*4882a593Smuzhiyun #define AM4_UART5_CLKCTRL AM4_CLKCTRL_INDEX(0x598) 100*4882a593Smuzhiyun #define AM4_UART6_CLKCTRL AM4_CLKCTRL_INDEX(0x5a0) 101*4882a593Smuzhiyun #define AM4_OCP2SCP0_CLKCTRL AM4_CLKCTRL_INDEX(0x5b8) 102*4882a593Smuzhiyun #define AM4_OCP2SCP1_CLKCTRL AM4_CLKCTRL_INDEX(0x5c0) 103*4882a593Smuzhiyun #define AM4_EMIF_CLKCTRL AM4_CLKCTRL_INDEX(0x720) 104*4882a593Smuzhiyun #define AM4_DSS_CORE_CLKCTRL AM4_CLKCTRL_INDEX(0xa20) 105*4882a593Smuzhiyun #define AM4_CPGMAC0_CLKCTRL AM4_CLKCTRL_INDEX(0xb20) 106*4882a593Smuzhiyun 107*4882a593Smuzhiyun /* XXX: Compatibility part end. */ 108*4882a593Smuzhiyun 109*4882a593Smuzhiyun /* l3s_tsc clocks */ 110*4882a593Smuzhiyun #define AM4_L3S_TSC_CLKCTRL_OFFSET 0x120 111*4882a593Smuzhiyun #define AM4_L3S_TSC_CLKCTRL_INDEX(offset) ((offset) - AM4_L3S_TSC_CLKCTRL_OFFSET) 112*4882a593Smuzhiyun #define AM4_L3S_TSC_ADC_TSC_CLKCTRL AM4_L3S_TSC_CLKCTRL_INDEX(0x120) 113*4882a593Smuzhiyun 114*4882a593Smuzhiyun /* l4_wkup_aon clocks */ 115*4882a593Smuzhiyun #define AM4_L4_WKUP_AON_CLKCTRL_OFFSET 0x228 116*4882a593Smuzhiyun #define AM4_L4_WKUP_AON_CLKCTRL_INDEX(offset) ((offset) - AM4_L4_WKUP_AON_CLKCTRL_OFFSET) 117*4882a593Smuzhiyun #define AM4_L4_WKUP_AON_WKUP_M3_CLKCTRL AM4_L4_WKUP_AON_CLKCTRL_INDEX(0x228) 118*4882a593Smuzhiyun #define AM4_L4_WKUP_AON_COUNTER_32K_CLKCTRL AM4_L4_WKUP_AON_CLKCTRL_INDEX(0x230) 119*4882a593Smuzhiyun 120*4882a593Smuzhiyun /* l4_wkup clocks */ 121*4882a593Smuzhiyun #define AM4_L4_WKUP_CLKCTRL_OFFSET 0x220 122*4882a593Smuzhiyun #define AM4_L4_WKUP_CLKCTRL_INDEX(offset) ((offset) - AM4_L4_WKUP_CLKCTRL_OFFSET) 123*4882a593Smuzhiyun #define AM4_L4_WKUP_L4_WKUP_CLKCTRL AM4_L4_WKUP_CLKCTRL_INDEX(0x220) 124*4882a593Smuzhiyun #define AM4_L4_WKUP_TIMER1_CLKCTRL AM4_L4_WKUP_CLKCTRL_INDEX(0x328) 125*4882a593Smuzhiyun #define AM4_L4_WKUP_WD_TIMER2_CLKCTRL AM4_L4_WKUP_CLKCTRL_INDEX(0x338) 126*4882a593Smuzhiyun #define AM4_L4_WKUP_I2C1_CLKCTRL AM4_L4_WKUP_CLKCTRL_INDEX(0x340) 127*4882a593Smuzhiyun #define AM4_L4_WKUP_UART1_CLKCTRL AM4_L4_WKUP_CLKCTRL_INDEX(0x348) 128*4882a593Smuzhiyun #define AM4_L4_WKUP_SMARTREFLEX0_CLKCTRL AM4_L4_WKUP_CLKCTRL_INDEX(0x350) 129*4882a593Smuzhiyun #define AM4_L4_WKUP_SMARTREFLEX1_CLKCTRL AM4_L4_WKUP_CLKCTRL_INDEX(0x358) 130*4882a593Smuzhiyun #define AM4_L4_WKUP_CONTROL_CLKCTRL AM4_L4_WKUP_CLKCTRL_INDEX(0x360) 131*4882a593Smuzhiyun #define AM4_L4_WKUP_GPIO1_CLKCTRL AM4_L4_WKUP_CLKCTRL_INDEX(0x368) 132*4882a593Smuzhiyun 133*4882a593Smuzhiyun /* mpu clocks */ 134*4882a593Smuzhiyun #define AM4_MPU_MPU_CLKCTRL AM4_CLKCTRL_INDEX(0x20) 135*4882a593Smuzhiyun 136*4882a593Smuzhiyun /* gfx_l3 clocks */ 137*4882a593Smuzhiyun #define AM4_GFX_L3_GFX_CLKCTRL AM4_CLKCTRL_INDEX(0x20) 138*4882a593Smuzhiyun 139*4882a593Smuzhiyun /* l4_rtc clocks */ 140*4882a593Smuzhiyun #define AM4_L4_RTC_RTC_CLKCTRL AM4_CLKCTRL_INDEX(0x20) 141*4882a593Smuzhiyun 142*4882a593Smuzhiyun /* l3 clocks */ 143*4882a593Smuzhiyun #define AM4_L3_L3_MAIN_CLKCTRL AM4_CLKCTRL_INDEX(0x20) 144*4882a593Smuzhiyun #define AM4_L3_AES_CLKCTRL AM4_CLKCTRL_INDEX(0x28) 145*4882a593Smuzhiyun #define AM4_L3_DES_CLKCTRL AM4_CLKCTRL_INDEX(0x30) 146*4882a593Smuzhiyun #define AM4_L3_L3_INSTR_CLKCTRL AM4_CLKCTRL_INDEX(0x40) 147*4882a593Smuzhiyun #define AM4_L3_OCMCRAM_CLKCTRL AM4_CLKCTRL_INDEX(0x50) 148*4882a593Smuzhiyun #define AM4_L3_SHAM_CLKCTRL AM4_CLKCTRL_INDEX(0x58) 149*4882a593Smuzhiyun #define AM4_L3_TPCC_CLKCTRL AM4_CLKCTRL_INDEX(0x78) 150*4882a593Smuzhiyun #define AM4_L3_TPTC0_CLKCTRL AM4_CLKCTRL_INDEX(0x80) 151*4882a593Smuzhiyun #define AM4_L3_TPTC1_CLKCTRL AM4_CLKCTRL_INDEX(0x88) 152*4882a593Smuzhiyun #define AM4_L3_TPTC2_CLKCTRL AM4_CLKCTRL_INDEX(0x90) 153*4882a593Smuzhiyun #define AM4_L3_L4_HS_CLKCTRL AM4_CLKCTRL_INDEX(0xa0) 154*4882a593Smuzhiyun 155*4882a593Smuzhiyun /* l3s clocks */ 156*4882a593Smuzhiyun #define AM4_L3S_CLKCTRL_OFFSET 0x68 157*4882a593Smuzhiyun #define AM4_L3S_CLKCTRL_INDEX(offset) ((offset) - AM4_L3S_CLKCTRL_OFFSET) 158*4882a593Smuzhiyun #define AM4_L3S_VPFE0_CLKCTRL AM4_L3S_CLKCTRL_INDEX(0x68) 159*4882a593Smuzhiyun #define AM4_L3S_VPFE1_CLKCTRL AM4_L3S_CLKCTRL_INDEX(0x70) 160*4882a593Smuzhiyun #define AM4_L3S_GPMC_CLKCTRL AM4_L3S_CLKCTRL_INDEX(0x220) 161*4882a593Smuzhiyun #define AM4_L3S_MCASP0_CLKCTRL AM4_L3S_CLKCTRL_INDEX(0x238) 162*4882a593Smuzhiyun #define AM4_L3S_MCASP1_CLKCTRL AM4_L3S_CLKCTRL_INDEX(0x240) 163*4882a593Smuzhiyun #define AM4_L3S_MMC3_CLKCTRL AM4_L3S_CLKCTRL_INDEX(0x248) 164*4882a593Smuzhiyun #define AM4_L3S_QSPI_CLKCTRL AM4_L3S_CLKCTRL_INDEX(0x258) 165*4882a593Smuzhiyun #define AM4_L3S_USB_OTG_SS0_CLKCTRL AM4_L3S_CLKCTRL_INDEX(0x260) 166*4882a593Smuzhiyun #define AM4_L3S_USB_OTG_SS1_CLKCTRL AM4_L3S_CLKCTRL_INDEX(0x268) 167*4882a593Smuzhiyun 168*4882a593Smuzhiyun /* pruss_ocp clocks */ 169*4882a593Smuzhiyun #define AM4_PRUSS_OCP_CLKCTRL_OFFSET 0x320 170*4882a593Smuzhiyun #define AM4_PRUSS_OCP_CLKCTRL_INDEX(offset) ((offset) - AM4_PRUSS_OCP_CLKCTRL_OFFSET) 171*4882a593Smuzhiyun #define AM4_PRUSS_OCP_PRUSS_CLKCTRL AM4_PRUSS_OCP_CLKCTRL_INDEX(0x320) 172*4882a593Smuzhiyun 173*4882a593Smuzhiyun /* l4ls clocks */ 174*4882a593Smuzhiyun #define AM4_L4LS_CLKCTRL_OFFSET 0x420 175*4882a593Smuzhiyun #define AM4_L4LS_CLKCTRL_INDEX(offset) ((offset) - AM4_L4LS_CLKCTRL_OFFSET) 176*4882a593Smuzhiyun #define AM4_L4LS_L4_LS_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x420) 177*4882a593Smuzhiyun #define AM4_L4LS_D_CAN0_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x428) 178*4882a593Smuzhiyun #define AM4_L4LS_D_CAN1_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x430) 179*4882a593Smuzhiyun #define AM4_L4LS_EPWMSS0_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x438) 180*4882a593Smuzhiyun #define AM4_L4LS_EPWMSS1_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x440) 181*4882a593Smuzhiyun #define AM4_L4LS_EPWMSS2_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x448) 182*4882a593Smuzhiyun #define AM4_L4LS_EPWMSS3_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x450) 183*4882a593Smuzhiyun #define AM4_L4LS_EPWMSS4_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x458) 184*4882a593Smuzhiyun #define AM4_L4LS_EPWMSS5_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x460) 185*4882a593Smuzhiyun #define AM4_L4LS_ELM_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x468) 186*4882a593Smuzhiyun #define AM4_L4LS_GPIO2_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x478) 187*4882a593Smuzhiyun #define AM4_L4LS_GPIO3_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x480) 188*4882a593Smuzhiyun #define AM4_L4LS_GPIO4_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x488) 189*4882a593Smuzhiyun #define AM4_L4LS_GPIO5_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x490) 190*4882a593Smuzhiyun #define AM4_L4LS_GPIO6_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x498) 191*4882a593Smuzhiyun #define AM4_L4LS_HDQ1W_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x4a0) 192*4882a593Smuzhiyun #define AM4_L4LS_I2C2_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x4a8) 193*4882a593Smuzhiyun #define AM4_L4LS_I2C3_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x4b0) 194*4882a593Smuzhiyun #define AM4_L4LS_MAILBOX_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x4b8) 195*4882a593Smuzhiyun #define AM4_L4LS_MMC1_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x4c0) 196*4882a593Smuzhiyun #define AM4_L4LS_MMC2_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x4c8) 197*4882a593Smuzhiyun #define AM4_L4LS_RNG_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x4e0) 198*4882a593Smuzhiyun #define AM4_L4LS_SPI0_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x500) 199*4882a593Smuzhiyun #define AM4_L4LS_SPI1_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x508) 200*4882a593Smuzhiyun #define AM4_L4LS_SPI2_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x510) 201*4882a593Smuzhiyun #define AM4_L4LS_SPI3_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x518) 202*4882a593Smuzhiyun #define AM4_L4LS_SPI4_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x520) 203*4882a593Smuzhiyun #define AM4_L4LS_SPINLOCK_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x528) 204*4882a593Smuzhiyun #define AM4_L4LS_TIMER2_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x530) 205*4882a593Smuzhiyun #define AM4_L4LS_TIMER3_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x538) 206*4882a593Smuzhiyun #define AM4_L4LS_TIMER4_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x540) 207*4882a593Smuzhiyun #define AM4_L4LS_TIMER5_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x548) 208*4882a593Smuzhiyun #define AM4_L4LS_TIMER6_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x550) 209*4882a593Smuzhiyun #define AM4_L4LS_TIMER7_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x558) 210*4882a593Smuzhiyun #define AM4_L4LS_TIMER8_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x560) 211*4882a593Smuzhiyun #define AM4_L4LS_TIMER9_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x568) 212*4882a593Smuzhiyun #define AM4_L4LS_TIMER10_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x570) 213*4882a593Smuzhiyun #define AM4_L4LS_TIMER11_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x578) 214*4882a593Smuzhiyun #define AM4_L4LS_UART2_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x580) 215*4882a593Smuzhiyun #define AM4_L4LS_UART3_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x588) 216*4882a593Smuzhiyun #define AM4_L4LS_UART4_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x590) 217*4882a593Smuzhiyun #define AM4_L4LS_UART5_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x598) 218*4882a593Smuzhiyun #define AM4_L4LS_UART6_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x5a0) 219*4882a593Smuzhiyun #define AM4_L4LS_OCP2SCP0_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x5b8) 220*4882a593Smuzhiyun #define AM4_L4LS_OCP2SCP1_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x5c0) 221*4882a593Smuzhiyun 222*4882a593Smuzhiyun /* emif clocks */ 223*4882a593Smuzhiyun #define AM4_EMIF_CLKCTRL_OFFSET 0x720 224*4882a593Smuzhiyun #define AM4_EMIF_CLKCTRL_INDEX(offset) ((offset) - AM4_EMIF_CLKCTRL_OFFSET) 225*4882a593Smuzhiyun #define AM4_EMIF_EMIF_CLKCTRL AM4_EMIF_CLKCTRL_INDEX(0x720) 226*4882a593Smuzhiyun 227*4882a593Smuzhiyun /* dss clocks */ 228*4882a593Smuzhiyun #define AM4_DSS_CLKCTRL_OFFSET 0xa20 229*4882a593Smuzhiyun #define AM4_DSS_CLKCTRL_INDEX(offset) ((offset) - AM4_DSS_CLKCTRL_OFFSET) 230*4882a593Smuzhiyun #define AM4_DSS_DSS_CORE_CLKCTRL AM4_DSS_CLKCTRL_INDEX(0xa20) 231*4882a593Smuzhiyun 232*4882a593Smuzhiyun /* cpsw_125mhz clocks */ 233*4882a593Smuzhiyun #define AM4_CPSW_125MHZ_CLKCTRL_OFFSET 0xb20 234*4882a593Smuzhiyun #define AM4_CPSW_125MHZ_CLKCTRL_INDEX(offset) ((offset) - AM4_CPSW_125MHZ_CLKCTRL_OFFSET) 235*4882a593Smuzhiyun #define AM4_CPSW_125MHZ_CPGMAC0_CLKCTRL AM4_CPSW_125MHZ_CLKCTRL_INDEX(0xb20) 236*4882a593Smuzhiyun 237*4882a593Smuzhiyun #endif 238