1 /* 2 * (C) Copyright 2018 Rockchip Electronics Co., Ltd. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 #ifndef _ASM_ARCH_GRF_rk3308_H 7 #define _ASM_ARCH_GRF_rk3308_H 8 9 #include <common.h> 10 11 struct rk3308_grf { 12 unsigned int gpio0a_iomux; 13 unsigned int reserved0; 14 unsigned int gpio0b_iomux; 15 unsigned int reserved1; 16 unsigned int gpio0c_iomux; 17 unsigned int reserved2[3]; 18 unsigned int gpio1a_iomux; 19 unsigned int reserved3; 20 unsigned int gpio1bl_iomux; 21 unsigned int gpio1bh_iomux; 22 unsigned int gpio1cl_iomux; 23 unsigned int gpio1ch_iomux; 24 unsigned int gpio1d_iomux; 25 unsigned int reserved4; 26 unsigned int gpio2a_iomux; 27 unsigned int reserved5; 28 unsigned int gpio2b_iomux; 29 unsigned int reserved6; 30 unsigned int gpio2c_iomux; 31 unsigned int reserved7[3]; 32 unsigned int gpio3a_iomux; 33 unsigned int reserved8; 34 unsigned int gpio3b_iomux; 35 unsigned int reserved9[5]; 36 unsigned int gpio4a_iomux; 37 unsigned int reserved33; 38 unsigned int gpio4b_iomux; 39 unsigned int reserved10; 40 unsigned int gpio4c_iomux; 41 unsigned int reserved11; 42 unsigned int gpio4d_iomux; 43 unsigned int reserved34; 44 unsigned int gpio0a_p; 45 unsigned int gpio0b_p; 46 unsigned int gpio0c_p; 47 unsigned int reserved12; 48 unsigned int gpio1a_p; 49 unsigned int gpio1b_p; 50 unsigned int gpio1c_p; 51 unsigned int gpio1d_p; 52 unsigned int gpio2a_p; 53 unsigned int gpio2b_p; 54 unsigned int gpio2c_p; 55 unsigned int reserved13; 56 unsigned int gpio3a_p; 57 unsigned int gpio3b_p; 58 unsigned int reserved14[2]; 59 unsigned int gpio4a_p; 60 unsigned int gpio4b_p; 61 unsigned int gpio4c_p; 62 unsigned int gpio4d_p; 63 unsigned int reserved15[(0x100 - 0xec) / 4 - 1]; 64 unsigned int gpio0a_e; 65 unsigned int gpio0b_e; 66 unsigned int gpio0c_e; 67 unsigned int reserved16; 68 unsigned int gpio1a_e; 69 unsigned int gpio1b_e; 70 unsigned int gpio1c_e; 71 unsigned int gpio1d_e; 72 unsigned int gpio2a_e; 73 unsigned int gpio2b_e; 74 unsigned int gpio2c_e; 75 unsigned int reserved17; 76 unsigned int gpio3a_e; 77 unsigned int gpio3b_e; 78 unsigned int reserved18[2]; 79 unsigned int gpio4a_e; 80 unsigned int gpio4b_e; 81 unsigned int gpio4c_e; 82 unsigned int gpio4d_e; 83 unsigned int gpio0a_sr; 84 unsigned int gpio0b_sr; 85 unsigned int gpio0c_sr; 86 unsigned int reserved19; 87 unsigned int gpio1a_sr; 88 unsigned int gpio1b_sr; 89 unsigned int gpio1c_sr; 90 unsigned int gpio1d_sr; 91 unsigned int gpio2a_sr; 92 unsigned int gpio2b_sr; 93 unsigned int gpio2c_sr; 94 unsigned int reserved20; 95 unsigned int gpio3a_sr; 96 unsigned int gpio3b_sr; 97 unsigned int reserved21[2]; 98 unsigned int gpio4a_sr; 99 unsigned int gpio4b_sr; 100 unsigned int gpio4c_sr; 101 unsigned int gpio4d_sr; 102 unsigned int gpio0a_smt; 103 unsigned int gpio0b_smt; 104 unsigned int gpio0c_smt; 105 unsigned int reserved22; 106 unsigned int gpio1a_smt; 107 unsigned int gpio1b_smt; 108 unsigned int gpio1c_smt; 109 unsigned int gpio1d_smt; 110 unsigned int gpio2a_smt; 111 unsigned int gpio2b_smt; 112 unsigned int gpio2c_smt; 113 unsigned int reserved23; 114 unsigned int gpio3a_smt; 115 unsigned int gpio3b_smt; 116 unsigned int reserved35[2]; 117 unsigned int gpio4a_smt; 118 unsigned int gpio4b_smt; 119 unsigned int gpio4c_smt; 120 unsigned int gpio4d_smt; 121 unsigned int reserved24[(0x300 - 0x1EC) / 4 - 1]; 122 unsigned int soc_con0; 123 unsigned int soc_con1; 124 unsigned int soc_con2; 125 unsigned int soc_con3; 126 unsigned int soc_con4; 127 unsigned int soc_con5; 128 unsigned int soc_con6; 129 unsigned int soc_con7; 130 unsigned int soc_con8; 131 unsigned int soc_con9; 132 unsigned int soc_con10; 133 unsigned int reserved25[(0x380 - 0x328) / 4 - 1]; 134 unsigned int soc_status0; 135 unsigned int reserved26[(0x400 - 0x380) / 4 - 1]; 136 unsigned int cpu_con0; 137 unsigned int cpu_con1; 138 unsigned int cpu_con2; 139 unsigned int reserved27[(0x420 - 0x408) / 4 - 1]; 140 unsigned int cpu_status0; 141 unsigned int cpu_status1; 142 unsigned int reserved28[(0x440 - 0x424) / 4 - 1]; 143 unsigned int pvtm_con0; 144 unsigned int pvtm_con1; 145 unsigned int pvtm_status0; 146 unsigned int pvtm_status1; 147 unsigned int reserved29[(0x460 - 0x44C) / 4 - 1]; 148 unsigned int tsadc_tbl; 149 unsigned int tsadc_tbh; 150 unsigned int reserved30[(0x480 - 0x464) / 4 - 1]; 151 unsigned int host0_con0; 152 unsigned int host0_con1; 153 unsigned int otg_con0; 154 unsigned int host0_status0; 155 unsigned int reserved31[(0x4a0 - 0x48C) / 4 - 1]; 156 unsigned int mac_con0; 157 unsigned int upctl_con0; 158 unsigned int upctl_status0; 159 unsigned int reserved32[(0x500 - 0x4A8) / 4 - 1]; 160 unsigned int os_reg0; 161 unsigned int os_reg1; 162 unsigned int os_reg2; 163 unsigned int os_reg3; 164 unsigned int os_reg4; 165 unsigned int os_reg5; 166 unsigned int os_reg6; 167 unsigned int os_reg7; 168 unsigned int os_reg8; 169 unsigned int os_reg9; 170 unsigned int os_reg10; 171 unsigned int os_reg11; 172 unsigned int reserved38[(0x600 - 0x52c) / 4 - 1]; 173 unsigned int soc_con12; 174 unsigned int reserved39; 175 unsigned int soc_con13; 176 unsigned int soc_con14; 177 unsigned int soc_con15; 178 unsigned int reserved40[(0x800 - 0x610) / 4 - 1]; 179 unsigned int chip_id; 180 }; 181 check_member(rk3308_grf, gpio0a_p, 0xa0); 182 183 struct rk3308_sgrf { 184 unsigned int soc_con0; 185 unsigned int soc_con1; 186 unsigned int con_tzma_r0size; 187 unsigned int con_secure0; 188 unsigned int reserved0; 189 unsigned int clk_timer_en; 190 unsigned int clkgat_con; 191 unsigned int fastboot_addr; 192 unsigned int fastboot_en; 193 unsigned int reserved1[(0x30 - 0x24) / 4]; 194 unsigned int srst_con; 195 }; 196 check_member(rk3308_sgrf, fastboot_en, 0x20); 197 198 enum { 199 /* GPIO0B_IOMUX */ 200 GPIO0B_SEL_SHIFT = 0x0, 201 GPIO0B_SEL_MASK = 0x3 << GPIO0B_SEL_SHIFT, 202 203 /* GPIO1D_IOMUX */ 204 GPIO1D1_SEL_SHIFT = 2, 205 GPIO1D1_SEL_MASK = 0x3 << GPIO1D1_SEL_SHIFT, 206 GPIO1D1_SEL_UART1_TX = 1, 207 GPIO1D0_SEL_SHIFT = 0, 208 GPIO1D0_SEL_MASK = 0x3 << GPIO1D0_SEL_SHIFT, 209 GPIO1D1_SEL_UART1_RX = 1, 210 211 /* GPIO2A_IOMUX */ 212 GPIO2A1_SEL_SHIFT = 2, 213 GPIO2A1_SEL_MASK = 0x3 << GPIO2A1_SEL_SHIFT, 214 GPIO2A1_SEL_UART0_TX = 1, 215 GPIO2A0_SEL_SHIFT = 0, 216 GPIO2A0_SEL_MASK = 0x3 << GPIO2A0_SEL_SHIFT, 217 GPIO2A0_SEL_UART0_RX = 1, 218 219 /* GPIO3B_IOMUX */ 220 GPIO3B5_SEL_SHIFT = 12, 221 GPIO3B5_SEL_MASK = 0xf << GPIO3B5_SEL_SHIFT, 222 GPIO3B5_SEL_UART3_TX = 4, 223 GPIO3B4_SEL_SHIFT = 8, 224 GPIO3B4_SEL_MASK = 0xf << GPIO3B4_SEL_SHIFT, 225 GPIO3B4_SEL_UART3_RX = 4, 226 227 /* GPIO4B_IOMUX */ 228 GPIO4B1_SEL_SHIFT = 2, 229 GPIO4B1_SEL_MASK = 0x3 << GPIO4B1_SEL_SHIFT, 230 GPIO4B1_SEL_UART4_TX = 1, 231 GPIO4B0_SEL_SHIFT = 0, 232 GPIO4B0_SEL_MASK = 0x3 << GPIO4B0_SEL_SHIFT, 233 GPIO4B0_SEL_UART4_RX = 1, 234 235 /* GPIO4D_IOMUX */ 236 GPIO4D3_SEL_SHIFT = 6, 237 GPIO4D3_SEL_MASK = 0x3 << GPIO4D3_SEL_SHIFT, 238 GPIO4D3_SEL_UART2_TXM1 = 2, 239 GPIO4D2_SEL_SHIFT = 4, 240 GPIO4D2_SEL_MASK = 0x3 << GPIO4D2_SEL_SHIFT, 241 GPIO4D2_SEL_UART2_RXM1 = 2, 242 243 /* PVTM_CON0 */ 244 PVTM_PMU_OSC_EN_SHIFT = 1, 245 PVTM_PMU_OSC_EN_MASK = 0x1 << PVTM_PMU_OSC_EN_SHIFT, 246 PVTM_PMU_OSC_EN = 1, 247 248 PVTM_PMU_START_SHIFT = 0, 249 PVTM_PMU_START_MASK = 0x1 << PVTM_PMU_START_SHIFT, 250 PVTM_PMU_START = 1, 251 252 /* PVTM_CON1 */ 253 PVTM_PMU_CAL_CNT = 0x1234, 254 255 /* PVTM_STATUS0 */ 256 PVTM_PMU_FREQ_DONE_SHIFT = 0, 257 PVTM_PMU_FREQ_DONE_MASK = 0x1 << PVTM_PMU_FREQ_DONE_SHIFT, 258 259 /* UPCTL_CON0 */ 260 CYSYREQ_UPCTL_DDRSTDBY_SHIFT = 5, 261 CYSYREQ_UPCTL_DDRSTDBY_MASK = 1 << CYSYREQ_UPCTL_DDRSTDBY_SHIFT, 262 CYSYREQ_UPCTL_DDRSTDBY_EN = 1, 263 GRF_DDR_16BIT_EN_SHIFT = 0, 264 GRF_DDR_16BIT_EN_MASK = 1 << GRF_DDR_16BIT_EN_SHIFT, 265 GRF_DDR_16BIT_EN = 1, 266 267 /* UPCTL_STATUS0 */ 268 DFI_SCRAMBLE_KEY_READY_SHIFT = 21, 269 DFI_SCRAMBLE_KEY_READY_MASK = 0x1 << DFI_SCRAMBLE_KEY_READY_SHIFT, 270 271 /* SOC_CON5 */ 272 UART2_MULTI_IOFUNC_SEL_SHIFT = 2, 273 UART2_MULTI_IOFUNC_SEL_MASK = 0x3 << UART2_MULTI_IOFUNC_SEL_SHIFT, 274 UART2_MULTI_IOFUNC_SEL_M1 = 1, 275 276 /* SOC_CON12 */ 277 NOC_MSCH_MAIN_PARTIAL_SHIFT = 1, 278 NOC_MSCH_MAIN_PARTIAL_MASK = 0x1 << NOC_MSCH_MAIN_PARTIAL_SHIFT, 279 NOC_MSCH_MAIN_PARTIAL_EN = 1, 280 NOC_MSCH_MAINDDR3_SHIFT = 0, 281 NOC_MSCH_MAINDDR3_MASK = 0x1 << NOC_MSCH_MAINDDR3_SHIFT, 282 NOC_MSCH_MAINDDR3_EN = 1, 283 NOC_MSCH_MAINDDR3_DIS = 0, 284 }; 285 286 enum { /* SGRF_CON0 */ 287 DDR_DFI_SCRAMBLE_EN_SHIFT = 13, 288 DDR_DFI_SCRAMBLE_EN_MASK = 0x1 << DDR_DFI_SCRAMBLE_EN_SHIFT, 289 DDR_DFI_SCRAMBLE_EN = 1, 290 }; 291 #endif 292