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/OK3568_Linux_fs/u-boot/arch/mips/dts/
H A Dimg,boston.dts19 #size-cells = <0>;
21 cpu@0 {
24 reg = <0>;
29 memory@0 {
31 reg = <0x00000000 0x10000000>;
51 reg = <0x10000000 0x2000000>;
60 ranges = <0x02000000 0 0x40000000
61 0x40000000 0 0x40000000>;
63 interrupt-map-mask = <0 0 0 7>;
64 interrupt-map = <0 0 0 1 &pci0_intc 0>,
[all …]
/OK3568_Linux_fs/kernel/arch/mips/boot/dts/img/
H A Dboston.dts24 #size-cells = <0>;
26 cpu@0 {
29 reg = <0>;
34 memory@0 {
36 reg = <0x00000000 0x10000000>;
42 reg = <0x10000000 0x2000000>;
51 ranges = <0x02000000 0 0x40000000
52 0x40000000 0 0x40000000>;
54 bus-range = <0x00 0xff>;
56 interrupt-map-mask = <0 0 0 7>;
[all …]
/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/arm/mediatek/
H A Dmediatek,vdecsys.txt27 reg = <0 0x16000000 0 0x1000>;
/OK3568_Linux_fs/kernel/drivers/input/serio/
H A Di8042-snirm.h26 #define I8042_COMMAND_REG (kbd_iobase + 0x64UL)
27 #define I8042_DATA_REG (kbd_iobase + 0x60UL)
31 return readb(kbd_iobase + 0x60UL); in i8042_read_data()
36 return readb(kbd_iobase + 0x64UL); in i8042_read_status()
41 writeb(val, kbd_iobase + 0x60UL); in i8042_write_data()
46 writeb(val, kbd_iobase + 0x64UL); in i8042_write_command()
52 kbd_iobase = ioremap(0x16000000, 4); in i8042_platform_init()
56 kbd_iobase = ioremap(0x14000000, 4); in i8042_platform_init()
63 return 0; in i8042_platform_init()
/OK3568_Linux_fs/kernel/arch/mips/boot/dts/netlogic/
H A Dxlp_gvp.dts17 ranges = <0 0 0 0x18000000 0x04000000 // PCIe CFG
18 1 0 0 0x16000000 0x02000000>; // GBU chipselects
23 reg = <0 0x112100 0xa00>;
32 #address-cells = <0>;
34 reg = <0 0x110000 0x200>;
38 nor_flash@1,0 {
43 reg = <1 0 0x1000000>;
45 partition@0 {
47 reg = <0x0 0x100000>; /* 1M */
53 reg = <0x100000 0x100000>; /* 1M */
[all …]
H A Dxlp_rvp.dts17 ranges = <0 0 0 0x18000000 0x04000000 // PCIe CFG
18 1 0 0 0x16000000 0x02000000>; // GBU chipselects
23 reg = <0 0x112100 0xa00>;
32 #address-cells = <0>;
34 reg = <0 0x110000 0x200>;
38 nor_flash@1,0 {
43 reg = <1 0 0x1000000>;
45 partition@0 {
47 reg = <0x0 0x100000>; /* 1M */
53 reg = <0x100000 0x100000>; /* 1M */
[all …]
H A Dxlp_evp.dts17 ranges = <0 0 0 0x18000000 0x04000000 // PCIe CFG
18 1 0 0 0x16000000 0x02000000>; // GBU chipselects
23 reg = <0 0x30100 0xa00>;
33 reg = <0 0x31100 0xa00>;
43 #size-cells = <0>;
44 reg = <0 0x32100 0xa00>;
54 #size-cells = <0>;
55 reg = <0 0x33100 0xa00>;
64 reg = <0x68>;
69 reg = <0x4c>;
[all …]
H A Dxlp_svp.dts17 ranges = <0 0 0 0x18000000 0x04000000 // PCIe CFG
18 1 0 0 0x16000000 0x02000000>; // GBU chipselects
23 reg = <0 0x30100 0xa00>;
33 reg = <0 0x31100 0xa00>;
43 #size-cells = <0>;
44 reg = <0 0x32100 0xa00>;
54 #size-cells = <0>;
55 reg = <0 0x33100 0xa00>;
64 reg = <0x68>;
69 reg = <0x4c>;
[all …]
H A Dxlp_fvp.dts17 ranges = <0 0 0 0x18000000 0x04000000 // PCIe CFG
18 1 0 0 0x16000000 0x02000000>; // GBU chipselects
23 reg = <0 0x30100 0xa00>;
33 reg = <0 0x31100 0xa00>;
43 #size-cells = <0>;
44 reg = <0 0x37100 0x20>;
54 #size-cells = <0>;
55 reg = <0 0x37120 0x20>;
64 reg = <0x68>;
69 reg = <0x4c>;
[all …]
/OK3568_Linux_fs/kernel/arch/mips/include/asm/netlogic/xlr/
H A Diomap.h38 #define DEFAULT_NETLOGIC_IO_BASE CKSEG1ADDR(0x1ef00000)
39 #define NETLOGIC_IO_DDR2_CHN0_OFFSET 0x01000
40 #define NETLOGIC_IO_DDR2_CHN1_OFFSET 0x02000
41 #define NETLOGIC_IO_DDR2_CHN2_OFFSET 0x03000
42 #define NETLOGIC_IO_DDR2_CHN3_OFFSET 0x04000
43 #define NETLOGIC_IO_PIC_OFFSET 0x08000
44 #define NETLOGIC_IO_UART_0_OFFSET 0x14000
45 #define NETLOGIC_IO_UART_1_OFFSET 0x15100
47 #define NETLOGIC_IO_SIZE 0x1000
49 #define NETLOGIC_IO_BRIDGE_OFFSET 0x00000
[all …]
/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/memory-controllers/
H A Dingenic,nemc.yaml14 pattern: "^memory-controller@[0-9a-f]+$"
40 ".*@[0-9]+$":
91 reg = <0x13410000 0x10000>;
94 ranges = <1 0 0x1b000000 0x1000000>,
95 <2 0 0x1a000000 0x1000000>,
96 <3 0 0x19000000 0x1000000>,
97 <4 0 0x18000000 0x1000000>,
98 <5 0 0x17000000 0x1000000>,
99 <6 0 0x16000000 0x1000000>;
108 pinctrl-0 = <&pins_nemc_cs6>;
[all …]
/OK3568_Linux_fs/kernel/arch/mips/include/asm/txx9/
H A Drbtx4927.h32 #define RBTX4927_PCIMEM 0x08000000
33 #define RBTX4927_PCIMEM_SIZE 0x08000000
34 #define RBTX4927_PCIIO 0x16000000
35 #define RBTX4927_PCIIO_SIZE 0x01000000
37 #define RBTX4927_LED_ADDR (IO_BASE + TXX9_CE(2) + 0x00001000)
38 #define RBTX4927_IMASK_ADDR (IO_BASE + TXX9_CE(2) + 0x00002000)
39 #define RBTX4927_IMSTAT_ADDR (IO_BASE + TXX9_CE(2) + 0x00002006)
40 #define RBTX4927_SOFTINT_ADDR (IO_BASE + TXX9_CE(2) + 0x00003000)
41 #define RBTX4927_SOFTRESET_ADDR (IO_BASE + TXX9_CE(2) + 0x0000f000)
42 #define RBTX4927_SOFTRESETLOCK_ADDR (IO_BASE + TXX9_CE(2) + 0x0000f002)
[all …]
/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/mtd/
H A Dingenic,nand.yaml61 reg = <0x13410000 0x10000>;
64 ranges = <1 0 0x1b000000 0x1000000>,
65 <2 0 0x1a000000 0x1000000>,
66 <3 0 0x19000000 0x1000000>,
67 <4 0 0x18000000 0x1000000>,
68 <5 0 0x17000000 0x1000000>,
69 <6 0 0x16000000 0x1000000>;
75 reg = <1 0 0x1000000>;
78 #size-cells = <0>;
89 pinctrl-0 = <&pins_nemc>;
[all …]
/OK3568_Linux_fs/kernel/arch/arm/boot/dts/
H A Dintegrator.dtsi12 reg = <0x0 0x0>;
17 reg = <0x10000000 0x200>;
20 led@c.0 {
22 offset = <0x0c>;
23 mask = <0x01>;
32 reg = <0x12000000 0x100>;
36 reg = <0x13000000 0x100>;
42 reg = <0x13000100 0x100>;
48 reg = <0x13000200 0x100>;
57 reg = <0x14000000 0x100>;
[all …]
H A Dimx1.dtsi38 reg = <0x00223000 0x1000>;
42 #size-cells = <0>;
45 cpu@0 {
47 reg = <0>;
59 #clock-cells = <0>;
75 reg = <0x00200000 0x10000>;
80 reg = <0x00202000 0x1000>;
89 reg = <0x00203000 0x1000>;
98 reg = <0x00205000 0x1000>;
109 reg = <0x00206000 0x1000>;
[all …]
H A Datlas7.dtsi29 #size-cells = <0>;
31 cpu@0 {
34 reg = <0>;
46 #clock-cells = <0>;
52 #clock-cells = <0>;
60 interrupts = <0 29 4>, <0 82 4>;
67 ranges = <0x10000000 0x10000000 0xc0000000>;
73 reg = <0x10301000 0x1000>,
74 <0x10302000 0x0100>;
79 reg = <0x10E30020 0x4>;
[all …]
H A Dqcom-msm8960.dtsi18 #size-cells = <0>;
19 interrupts = <1 14 0x304>;
21 cpu@0 {
25 reg = <0>;
49 reg = <0x0 0x0>;
54 interrupts = <1 10 0x304>;
61 #clock-cells = <0>;
68 #clock-cells = <0>;
75 #clock-cells = <0>;
91 reg = <0x02000000 0x1000>,
[all …]
/OK3568_Linux_fs/kernel/arch/sh/boards/mach-se/7343/
H A Dsetup.c32 .offset = 0x00000000,
54 [0] = {
55 .start = 0x00000000,
56 .end = 0x01ffffff,
73 [0] = {
75 .mapbase = 0x16000000,
82 .mapbase = 0x17000000,
104 [0] = {
105 .start = 0x11800000,
106 .end = 0x11800001,
[all …]
/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/media/
H A Dmediatek-vcodec.txt32 reg = <0 0x16000000 0 0x100>, /*VDEC_SYS*/
33 <0 0x16020000 0 0x1000>, /*VDEC_MISC*/
34 <0 0x16021000 0 0x800>, /*VDEC_LD*/
35 <0 0x16021800 0 0x800>, /*VDEC_TOP*/
36 <0 0x16022000 0 0x1000>, /*VDEC_CM*/
37 <0 0x16023000 0 0x1000>, /*VDEC_AD*/
38 <0 0x16024000 0 0x1000>, /*VDEC_AV*/
39 <0 0x16025000 0 0x1000>, /*VDEC_PP*/
40 <0 0x16026800 0 0x800>, /*VP8_VD*/
41 <0 0x16027000 0 0x800>, /*VP6_VD*/
[all …]
/OK3568_Linux_fs/u-boot/board/armltd/integrator/
H A Dintegrator.c32 .base = 0x16000000,
38 .clock = 0, /* Not used for PL010 */
56 #define COMP_MODE_ENABLE ((unsigned int)0x0000EAEF)
74 gd->bd->bi_boot_params = 0x00000100; in board_init()
78 cm_remap(); /* remaps writeable memory to 0x00000000 */ in board_init()
103 writel(0, EBI_BASE + EBI_LOCK_REG); in board_init()
114 return 0; in board_init()
120 return (0); in misc_init_r()
124 * The Integrator remaps the Flash memory to 0x00000000 and executes U-Boot
130 #define REMAPPED_FLASH_SZ 0x40000
[all …]
/OK3568_Linux_fs/u-boot/arch/mips/mach-ath79/include/mach/
H A Dar71xx_regs.h23 #define AR71XX_APB_BASE 0x18000000
24 #define AR71XX_GE0_BASE 0x19000000
25 #define AR71XX_GE0_SIZE 0x10000
26 #define AR71XX_GE1_BASE 0x1a000000
27 #define AR71XX_GE1_SIZE 0x10000
28 #define AR71XX_EHCI_BASE 0x1b000000
29 #define AR71XX_EHCI_SIZE 0x1000
30 #define AR71XX_OHCI_BASE 0x1c000000
31 #define AR71XX_OHCI_SIZE 0x1000
32 #define AR71XX_SPI_BASE 0x1f000000
[all …]
/OK3568_Linux_fs/kernel/arch/mips/include/asm/mach-ath79/
H A Dar71xx_regs.h19 #define AR71XX_APB_BASE 0x18000000
20 #define AR71XX_GE0_BASE 0x19000000
21 #define AR71XX_GE0_SIZE 0x10000
22 #define AR71XX_GE1_BASE 0x1a000000
23 #define AR71XX_GE1_SIZE 0x10000
24 #define AR71XX_EHCI_BASE 0x1b000000
25 #define AR71XX_EHCI_SIZE 0x1000
26 #define AR71XX_OHCI_BASE 0x1c000000
27 #define AR71XX_OHCI_SIZE 0x1000
28 #define AR71XX_SPI_BASE 0x1f000000
[all …]
/OK3568_Linux_fs/kernel/arch/arm/mach-integrator/
H A Dhardware.h14 #define IO_BASE 0xF0000000 // VA of IO
15 #define IO_SIZE 0x0B000000 // How much?
20 #define IO_ADDRESS(x) (((x) & 0x000fffff) | (((x) >> 4) & 0x0ff00000) | IO_BASE)
30 #define INTEGRATOR_BOOT_ROM_LO 0x00000000
31 #define INTEGRATOR_BOOT_ROM_HI 0x20000000
45 #define INTEGRATOR_SSRAM_BASE 0x00000000
46 #define INTEGRATOR_SSRAM_ALIAS_BASE 0x10800000
49 #define INTEGRATOR_FLASH_BASE 0x24000000
52 #define INTEGRATOR_MBRD_SSRAM_BASE 0x28000000
58 #define INTEGRATOR_SDRAM_BASE 0x00040000
[all …]
/OK3568_Linux_fs/u-boot/drivers/ddr/marvell/a38x/
H A Dddr3_training_ip_flow.h13 #define MRS0_CMD 0x3
14 #define MRS1_CMD 0x4
15 #define MRS2_CMD 0x8
16 #define MRS3_CMD 0x9
22 #define READ_BUFFER_SELECT 0x14a4
35 if (IS_ACTIVE(mask, id) == 0) \
43 (((if_mask) == 0xb) ? 1 : 0)
45 (((((if_mask) & 0x10) == 0)) ? 0 : 1)
47 (((((mask) & 0x4) == 0)) ? 1 : 0)
56 * [31 : 20] 0x? DFX base address bases PCIe mapping
[all …]
/OK3568_Linux_fs/kernel/fs/freevxfs/
H A Dvxfs.h45 #define VXFS_SUPER_MAGIC 0xa501FCF5
201 * File modes. File types above 0xf000 are vxfs internal only, they should
206 VXFS_ISUID = 0x00000800, /* setuid */
207 VXFS_ISGID = 0x00000400, /* setgid */
208 VXFS_ISVTX = 0x00000200, /* sticky bit */
209 VXFS_IREAD = 0x00000100, /* read */
210 VXFS_IWRITE = 0x00000080, /* write */
211 VXFS_IEXEC = 0x00000040, /* exec */
213 VXFS_IFIFO = 0x00001000, /* Named pipe */
214 VXFS_IFCHR = 0x00002000, /* Character device */
[all …]

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