1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Author: MontaVista Software, Inc. 3*4882a593Smuzhiyun * source@mvista.com 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright 2001-2002 MontaVista Software Inc. 6*4882a593Smuzhiyun * 7*4882a593Smuzhiyun * This program is free software; you can redistribute it and/or modify it 8*4882a593Smuzhiyun * under the terms of the GNU General Public License as published by the 9*4882a593Smuzhiyun * Free Software Foundation; either version 2 of the License, or (at your 10*4882a593Smuzhiyun * option) any later version. 11*4882a593Smuzhiyun * 12*4882a593Smuzhiyun * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED 13*4882a593Smuzhiyun * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 14*4882a593Smuzhiyun * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 15*4882a593Smuzhiyun * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 16*4882a593Smuzhiyun * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 17*4882a593Smuzhiyun * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS 18*4882a593Smuzhiyun * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND 19*4882a593Smuzhiyun * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR 20*4882a593Smuzhiyun * TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE 21*4882a593Smuzhiyun * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 22*4882a593Smuzhiyun * 23*4882a593Smuzhiyun * You should have received a copy of the GNU General Public License along 24*4882a593Smuzhiyun * with this program; if not, write to the Free Software Foundation, Inc., 25*4882a593Smuzhiyun * 675 Mass Ave, Cambridge, MA 02139, USA. 26*4882a593Smuzhiyun */ 27*4882a593Smuzhiyun #ifndef __ASM_TXX9_RBTX4927_H 28*4882a593Smuzhiyun #define __ASM_TXX9_RBTX4927_H 29*4882a593Smuzhiyun 30*4882a593Smuzhiyun #include <asm/txx9/tx4927.h> 31*4882a593Smuzhiyun 32*4882a593Smuzhiyun #define RBTX4927_PCIMEM 0x08000000 33*4882a593Smuzhiyun #define RBTX4927_PCIMEM_SIZE 0x08000000 34*4882a593Smuzhiyun #define RBTX4927_PCIIO 0x16000000 35*4882a593Smuzhiyun #define RBTX4927_PCIIO_SIZE 0x01000000 36*4882a593Smuzhiyun 37*4882a593Smuzhiyun #define RBTX4927_LED_ADDR (IO_BASE + TXX9_CE(2) + 0x00001000) 38*4882a593Smuzhiyun #define RBTX4927_IMASK_ADDR (IO_BASE + TXX9_CE(2) + 0x00002000) 39*4882a593Smuzhiyun #define RBTX4927_IMSTAT_ADDR (IO_BASE + TXX9_CE(2) + 0x00002006) 40*4882a593Smuzhiyun #define RBTX4927_SOFTINT_ADDR (IO_BASE + TXX9_CE(2) + 0x00003000) 41*4882a593Smuzhiyun #define RBTX4927_SOFTRESET_ADDR (IO_BASE + TXX9_CE(2) + 0x0000f000) 42*4882a593Smuzhiyun #define RBTX4927_SOFTRESETLOCK_ADDR (IO_BASE + TXX9_CE(2) + 0x0000f002) 43*4882a593Smuzhiyun #define RBTX4927_PCIRESET_ADDR (IO_BASE + TXX9_CE(2) + 0x0000f006) 44*4882a593Smuzhiyun #define RBTX4927_BRAMRTC_BASE (IO_BASE + TXX9_CE(2) + 0x00010000) 45*4882a593Smuzhiyun #define RBTX4927_ETHER_BASE (IO_BASE + TXX9_CE(2) + 0x00020000) 46*4882a593Smuzhiyun 47*4882a593Smuzhiyun /* Ethernet port address */ 48*4882a593Smuzhiyun #define RBTX4927_ETHER_ADDR (RBTX4927_ETHER_BASE + 0x280) 49*4882a593Smuzhiyun 50*4882a593Smuzhiyun #define rbtx4927_imask_addr ((__u8 __iomem *)RBTX4927_IMASK_ADDR) 51*4882a593Smuzhiyun #define rbtx4927_imstat_addr ((__u8 __iomem *)RBTX4927_IMSTAT_ADDR) 52*4882a593Smuzhiyun #define rbtx4927_softint_addr ((__u8 __iomem *)RBTX4927_SOFTINT_ADDR) 53*4882a593Smuzhiyun #define rbtx4927_softreset_addr ((__u8 __iomem *)RBTX4927_SOFTRESET_ADDR) 54*4882a593Smuzhiyun #define rbtx4927_softresetlock_addr \ 55*4882a593Smuzhiyun ((__u8 __iomem *)RBTX4927_SOFTRESETLOCK_ADDR) 56*4882a593Smuzhiyun #define rbtx4927_pcireset_addr ((__u8 __iomem *)RBTX4927_PCIRESET_ADDR) 57*4882a593Smuzhiyun 58*4882a593Smuzhiyun /* bits for ISTAT/IMASK/IMSTAT */ 59*4882a593Smuzhiyun #define RBTX4927_INTB_PCID 0 60*4882a593Smuzhiyun #define RBTX4927_INTB_PCIC 1 61*4882a593Smuzhiyun #define RBTX4927_INTB_PCIB 2 62*4882a593Smuzhiyun #define RBTX4927_INTB_PCIA 3 63*4882a593Smuzhiyun #define RBTX4927_INTF_PCID (1 << RBTX4927_INTB_PCID) 64*4882a593Smuzhiyun #define RBTX4927_INTF_PCIC (1 << RBTX4927_INTB_PCIC) 65*4882a593Smuzhiyun #define RBTX4927_INTF_PCIB (1 << RBTX4927_INTB_PCIB) 66*4882a593Smuzhiyun #define RBTX4927_INTF_PCIA (1 << RBTX4927_INTB_PCIA) 67*4882a593Smuzhiyun 68*4882a593Smuzhiyun #define RBTX4927_NR_IRQ_IOC 8 /* IOC */ 69*4882a593Smuzhiyun 70*4882a593Smuzhiyun #define RBTX4927_IRQ_IOC (TXX9_IRQ_BASE + TX4927_NUM_IR) 71*4882a593Smuzhiyun #define RBTX4927_IRQ_IOC_PCID (RBTX4927_IRQ_IOC + RBTX4927_INTB_PCID) 72*4882a593Smuzhiyun #define RBTX4927_IRQ_IOC_PCIC (RBTX4927_IRQ_IOC + RBTX4927_INTB_PCIC) 73*4882a593Smuzhiyun #define RBTX4927_IRQ_IOC_PCIB (RBTX4927_IRQ_IOC + RBTX4927_INTB_PCIB) 74*4882a593Smuzhiyun #define RBTX4927_IRQ_IOC_PCIA (RBTX4927_IRQ_IOC + RBTX4927_INTB_PCIA) 75*4882a593Smuzhiyun 76*4882a593Smuzhiyun #define RBTX4927_IRQ_IOCINT (TXX9_IRQ_BASE + TX4927_IR_INT(1)) 77*4882a593Smuzhiyun 78*4882a593Smuzhiyun #ifdef CONFIG_PCI 79*4882a593Smuzhiyun #define RBTX4927_ISA_IO_OFFSET RBTX4927_PCIIO 80*4882a593Smuzhiyun #else 81*4882a593Smuzhiyun #define RBTX4927_ISA_IO_OFFSET 0 82*4882a593Smuzhiyun #endif 83*4882a593Smuzhiyun 84*4882a593Smuzhiyun #define RBTX4927_RTL_8019_BASE (RBTX4927_ETHER_ADDR - mips_io_port_base) 85*4882a593Smuzhiyun #define RBTX4927_RTL_8019_IRQ (TXX9_IRQ_BASE + TX4927_IR_INT(3)) 86*4882a593Smuzhiyun 87*4882a593Smuzhiyun void rbtx4927_prom_init(void); 88*4882a593Smuzhiyun void rbtx4927_irq_setup(void); 89*4882a593Smuzhiyun struct pci_dev; 90*4882a593Smuzhiyun int rbtx4927_pci_map_irq(const struct pci_dev *dev, u8 slot, u8 pin); 91*4882a593Smuzhiyun 92*4882a593Smuzhiyun #endif /* __ASM_TXX9_RBTX4927_H */ 93