| /OK3568_Linux_fs/kernel/drivers/video/fbdev/riva/ |
| H A D | riva_tbl.h | 55 {0x00000050, 0x00000000},
56 {0x00000080, 0xFFFF00FF},
57 {0x00000080, 0xFFFFFFFF}
61 {0x00000080, 0x00000008},
62 {0x00000084, 0x00000003},
63 {0x00000050, 0x00000000},
64 {0x00000040, 0xFFFFFFFF}
68 {0x00000000, 0x80000000},
69 {0x00000800, 0x80000001},
70 {0x00001000, 0x80000002},
[all …]
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| /OK3568_Linux_fs/kernel/include/linux/mfd/ |
| H A D | ezx-pcap.h | 40 #define PCAP_REGISTER_WRITE_OP_BIT 0x80000000
41 #define PCAP_REGISTER_READ_OP_BIT 0x00000000
43 #define PCAP_REGISTER_VALUE_MASK 0x01ffffff
44 #define PCAP_REGISTER_ADDRESS_MASK 0x7c000000
47 #define PCAP_CLEAR_INTERRUPT_REGISTER 0x01ffffff
48 #define PCAP_MASK_ALL_INTERRUPT 0x01ffffff
51 #define PCAP_REG_ISR 0x0 /* Interrupt Status */
52 #define PCAP_REG_MSR 0x1 /* Interrupt Mask */
53 #define PCAP_REG_PSTAT 0x2 /* Processor Status */
54 #define PCAP_REG_VREG2 0x6 /* Regulator Bank 2 Control */
[all …]
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| /OK3568_Linux_fs/kernel/Documentation/gpu/ |
| H A D | kms-properties.csv | 7 ,,“left margin”,RANGE,"Min=0, Max=100",Connector,TBD
8 ,,“right margin”,RANGE,"Min=0, Max=100",Connector,TBD
9 ,,“top margin”,RANGE,"Min=0, Max=100",Connector,TBD
10 ,,“bottom margin”,RANGE,"Min=0, Max=100",Connector,TBD
11 ,,“brightness”,RANGE,"Min=0, Max=100",Connector,TBD
12 ,,“contrast”,RANGE,"Min=0, Max=100",Connector,TBD
13 ,,“flicker reduction”,RANGE,"Min=0, Max=100",Connector,TBD
14 ,,“overscan”,RANGE,"Min=0, Max=100",Connector,TBD
15 ,,“saturation”,RANGE,"Min=0, Max=100",Connector,TBD
16 ,,“hue”,RANGE,"Min=0, Max=100",Connector,TBD
[all …]
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| /OK3568_Linux_fs/kernel/drivers/scsi/ |
| H A D | gvp11.c | 43 static int gvp11_xfer_mask = 0;
59 static int scsi_alloc_out_of_range = 0; in dma_setup()
63 wh->dma_bounce_len = (cmd->SCp.this_residual + 511) & ~0x1ff; in dma_setup()
78 wh->dma_bounce_len = 0; in dma_setup()
102 wh->dma_bounce_len = 0; in dma_setup()
135 bank_mask = (~wh->dma_xfer_mask >> 18) & 0x01c0; in dma_setup()
143 return 0; in dma_setup()
170 wh->dma_bounce_len = 0; in dma_stop()
215 if (q & 0x08) /* bit 3 should always be clear */ in check_wd33c93()
226 if (*scmd_3393 != q) /* and so should the image at 0x1f */ in check_wd33c93()
[all …]
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| /OK3568_Linux_fs/kernel/arch/arm/mach-pxa/include/mach/ |
| H A D | hardware.h | 19 #define UNCACHED_PHYS_0 0xfe000000
20 #define UNCACHED_PHYS_0_SIZE 0x00100000
25 * 0x40000000 - 0x41ffffff <--> 0xf2000000 - 0xf3ffffff
26 * 0x44000000 - 0x45ffffff <--> 0xf4000000 - 0xf5ffffff
27 * 0x48000000 - 0x49ffffff <--> 0xf6000000 - 0xf7ffffff
28 * 0x4c000000 - 0x4dffffff <--> 0xf8000000 - 0xf9ffffff
29 * 0x50000000 - 0x51ffffff <--> 0xfa000000 - 0xfbffffff
30 * 0x54000000 - 0x55ffffff <--> 0xfc000000 - 0xfdffffff
31 * 0x58000000 - 0x59ffffff <--> 0xfe000000 - 0xffffffff
36 #define io_v2p(x) (0x3c000000 + ((x) & 0x01ffffff) + (((x) & 0x0e000000) << 1))
[all …]
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| /OK3568_Linux_fs/u-boot/arch/arm/include/asm/arch-spear/ |
| H A D | spr_syscntl.h | 27 #define MODE_SHIFT 0x00000003
29 #define NORMAL 0x00000004
30 #define SLOW 0x00000002
31 #define DOZE 0x00000001
32 #define SLEEP 0x00000000
34 #define PLL_TIM 0x01FFFFFF
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| /OK3568_Linux_fs/external/xserver/hw/xquartz/ |
| H A D | keysym2ucs.h | 15 * U-00FFFFFF by a keysym value in the range 0x01000000 to 0x01ffffff.
20 * U+ABCD you can directly use keysym 0x0100abcd.
33 #define ARRAY_SIZE(a) (sizeof((a)) / sizeof((a)[0]))
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| /OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/watchdog/ |
| H A D | snps,dw-wdt.yaml | 52 default: [0x0001000 0x0002000 0x0004000 0x0008000
53 0x0010000 0x0020000 0x0040000 0x0080000
54 0x0100000 0x0200000 0x0400000 0x0800000
55 0x1000000 0x2000000 0x4000000 0x8000000]
70 reg = <0xffd02000 0x1000>;
71 interrupts = <0 171 4>;
79 reg = <0xffd02000 0x1000>;
80 interrupts = <0 171 4>;
83 snps,watchdog-tops = <0x000000FF 0x000001FF 0x000003FF
84 0x000007FF 0x0000FFFF 0x0001FFFF
[all …]
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| /OK3568_Linux_fs/kernel/arch/mips/alchemy/common/ |
| H A D | vss.c | 14 #define VSS_GATE 0x00 /* gate wait timers */
15 #define VSS_CLKRST 0x04 /* clock/block control */
16 #define VSS_FTR 0x08 /* footers */
18 #define VSS_ADDR(blk) (KSEG1ADDR(AU1300_VSS_PHYS_ADDR) + (blk * 0x0c))
30 __raw_writel(0x01fffffe, base + VSS_GATE); /* maximum setup time */ in __enable_block()
34 __raw_writel(0x01, base + VSS_FTR); in __enable_block()
36 __raw_writel(0x03, base + VSS_FTR); in __enable_block()
38 __raw_writel(0x07, base + VSS_FTR); in __enable_block()
40 __raw_writel(0x0f, base + VSS_FTR); in __enable_block()
43 __raw_writel(0x01ffffff, base + VSS_GATE); /* start FSM too */ in __enable_block()
[all …]
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| /OK3568_Linux_fs/kernel/arch/mips/cobalt/ |
| H A D | setup.c | 51 .start = 0x00,
52 .end = 0x1f,
57 .start = 0x60,
58 .end = 0x6f,
63 .start = 0x80,
64 .end = 0x8f,
69 .start = 0xc0,
70 .end = 0xdf,
87 ioport_resource.end = 0x01ffffff; in plat_mem_setup()
90 for (i = 0; i < ARRAY_SIZE(cobalt_reserved_resources); i++) in plat_mem_setup()
[all …]
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| /OK3568_Linux_fs/kernel/arch/m68k/mm/ |
| H A D | cache.c | 24 "1: plpar (%0)\n" in virt_to_phys_slow()
29 "3: sub.l %0,%0\n" in virt_to_phys_slow()
37 : "0" (vaddr)); in virt_to_phys_slow()
44 "movec %%mmusr, %0\n\t" in virt_to_phys_slow()
55 asm volatile ("ptestr %3,%2@,#7,%0\n\t" in virt_to_phys_slow()
60 return 0; in virt_to_phys_slow()
64 return (*descaddr & 0xfe000000) | (vaddr & 0x01ffffff); in virt_to_phys_slow()
66 return (*descaddr & 0xfffc0000) | (vaddr & 0x0003ffff); in virt_to_phys_slow()
71 return 0; in virt_to_phys_slow()
83 flush_cf_icache(0, end); in flush_icache_user_range()
[all …]
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| /OK3568_Linux_fs/kernel/arch/sh/boards/mach-se/7343/ |
| H A D | setup.c | 32 .offset = 0x00000000,
54 [0] = {
55 .start = 0x00000000,
56 .end = 0x01ffffff,
73 [0] = {
75 .mapbase = 0x16000000,
82 .mapbase = 0x17000000,
104 [0] = {
105 .start = 0x11800000,
106 .end = 0x11800001,
[all …]
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| /OK3568_Linux_fs/external/rkwifibt/drivers/rtl8852be/phl/hal_g6/phy/rf/halrf_8852b/ |
| H A D | halrf_psd_8852b.c | 28 for (i = 0; i < reg_num; i++) { in _halrf_psd_backup_bb_registers_8852b()
31 RF_DBG(rf, DBG_RF_PSD, "[TXGAPK] Backup BB 0x%08x = 0x%08x\n", in _halrf_psd_backup_bb_registers_8852b()
46 for (i = 0; i < reg_num; i++) { in _halrf_psd_reload_bb_registers_8852b()
49 RF_DBG(rf, DBG_RF_PSD, "[TXGAPK] Reload BB 0x%08x = 0x%08x\n", in _halrf_psd_reload_bb_registers_8852b()
59 0x20fc, 0x5864, 0x7864, 0x12b8, 0x32b8, in halrf_psd_init_8852b()
60 0x030c, 0x032c, 0x58c8, 0x78c8, 0x2008, in halrf_psd_init_8852b()
61 0x0c1c, 0x0700, 0x0c70, 0x0c60, 0x0c6c, in halrf_psd_init_8852b()
62 0x58ac, 0x78ac, 0x0c3c, 0x2320, 0x4490, in halrf_psd_init_8852b()
63 0x12a0, 0x32a0, 0x8008, 0x8080, 0x8088, in halrf_psd_init_8852b()
64 0x80d0, 0x8074, 0x81dc, 0x82dc, 0x8120, in halrf_psd_init_8852b()
[all …]
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| /OK3568_Linux_fs/external/rkwifibt/drivers/rtl8852bs/phl/hal_g6/phy/rf/halrf_8852b/ |
| H A D | halrf_psd_8852b.c | 28 for (i = 0; i < reg_num; i++) { in _halrf_psd_backup_bb_registers_8852b()
31 RF_DBG(rf, DBG_RF_PSD, "[TXGAPK] Backup BB 0x%08x = 0x%08x\n", in _halrf_psd_backup_bb_registers_8852b()
46 for (i = 0; i < reg_num; i++) { in _halrf_psd_reload_bb_registers_8852b()
49 RF_DBG(rf, DBG_RF_PSD, "[TXGAPK] Reload BB 0x%08x = 0x%08x\n", in _halrf_psd_reload_bb_registers_8852b()
59 0x20fc, 0x5864, 0x7864, 0x12b8, 0x32b8, in halrf_psd_init_8852b()
60 0x030c, 0x032c, 0x58c8, 0x78c8, 0x2008, in halrf_psd_init_8852b()
61 0x0c1c, 0x0700, 0x0c70, 0x0c60, 0x0c6c, in halrf_psd_init_8852b()
62 0x58ac, 0x78ac, 0x0c3c, 0x2320, 0x4490, in halrf_psd_init_8852b()
63 0x12a0, 0x32a0, 0x8008, 0x8080, 0x8088, in halrf_psd_init_8852b()
64 0x80d0, 0x8074, 0x81dc, 0x82dc, 0x8120, in halrf_psd_init_8852b()
[all …]
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| /OK3568_Linux_fs/kernel/drivers/media/platform/ti-vpe/ |
| H A D | sc.h | 13 #define CFG_SC0 0x0
14 #define CFG_INTERLACE_O (1 << 0)
30 #define CFG_SC1 0x4
31 #define CFG_ROW_ACC_INC_MASK 0x07ffffff
32 #define CFG_ROW_ACC_INC_SHIFT 0
34 #define CFG_SC2 0x08
35 #define CFG_ROW_ACC_OFFSET_MASK 0x0fffffff
36 #define CFG_ROW_ACC_OFFSET_SHIFT 0
38 #define CFG_SC3 0x0c
39 #define CFG_ROW_ACC_OFFSET_B_MASK 0x0fffffff
[all …]
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| /OK3568_Linux_fs/kernel/drivers/scsi/arm/ |
| H A D | oak.c | 51 while (((status = readw(base + STAT)) & 0x100)==0); in oakscsi_pwrite()
53 return 0; in oakscsi_pwrite()
62 while(len > 0) in oakscsi_pread()
67 timeout = 0x01FFFFFF; in oakscsi_pread()
69 while (((status = readw(base + STAT)) & 0x100)==0) in oakscsi_pread()
72 if(status & 0x200 || !timeout) in oakscsi_pread()
95 return 0; in oakscsi_pread()
185 { 0xffff, 0xffff }
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| /OK3568_Linux_fs/kernel/drivers/gpu/drm/radeon/ |
| H A D | nislands_smc.h | 125 #define NISLANDS_SMC_STROBE_RATIO 0x0F
126 #define NISLANDS_SMC_STROBE_ENABLE 0x10
128 #define NISLANDS_SMC_MC_EDC_RD_FLAG 0x01
129 #define NISLANDS_SMC_MC_EDC_WR_FLAG 0x02
130 #define NISLANDS_SMC_MC_RTT_ENABLE 0x04
131 #define NISLANDS_SMC_MC_STUTTER_EN 0x08
146 #define NISLANDS_SMC_VOLTAGEMASK_VDDC 0
180 #define NI_SMC_SOFT_REGISTERS_START 0x108
182 #define NI_SMC_SOFT_REGISTER_mclk_chg_timeout 0x0
183 #define NI_SMC_SOFT_REGISTER_delay_bbias 0xC
[all …]
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| H A D | sislands_smc.h | 172 #define SISLANDS_SMC_STROBE_RATIO 0x0F
173 #define SISLANDS_SMC_STROBE_ENABLE 0x10
175 #define SISLANDS_SMC_MC_EDC_RD_FLAG 0x01
176 #define SISLANDS_SMC_MC_EDC_WR_FLAG 0x02
177 #define SISLANDS_SMC_MC_RTT_ENABLE 0x04
178 #define SISLANDS_SMC_MC_STUTTER_EN 0x08
179 #define SISLANDS_SMC_MC_PG_EN 0x10
194 #define SISLANDS_SMC_VOLTAGEMASK_VDDC 0
228 #define SI_SMC_SOFT_REGISTER_mclk_chg_timeout 0x0
229 #define SI_SMC_SOFT_REGISTER_delay_vreg 0xC
[all …]
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| /OK3568_Linux_fs/kernel/drivers/gpu/drm/nouveau/dispnv04/ |
| H A D | overlay.c | 71 * Note that this only works for the range [0, 180].
103 if (src_x != 0 || src_y != 0) { in verify_scaling()
109 return 0; in verify_scaling()
130 unsigned shift = drm->client.device.info.chipset >= 0x30 ? 1 : 3; in nv10_update_plane()
131 unsigned format = 0; in nv10_update_plane()
140 ret = verify_scaling(fb, shift, 0, 0, src_w, src_h, crtc_w, crtc_h); in nv10_update_plane()
144 nvbo = nouveau_gem_object(fb->obj[0]); in nv10_update_plane()
152 nvif_mask(dev, NV_PCRTC_ENGINE_CTRL + soff2, NV_CRTC_FSEL_OVERLAY, 0); in nv10_update_plane()
154 nvif_wr32(dev, NV_PVIDEO_BASE(flip), 0); in nv10_update_plane()
175 nvif_wr32(dev, NV_PVIDEO_UVPLANE_BASE(flip), 0); in nv10_update_plane()
[all …]
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| /OK3568_Linux_fs/u-boot/include/configs/ |
| H A D | edb93xx.h | 39 #define CONFIG_ENV_SECT_SIZE 0x00020000
43 #define CONFIG_ENV_SECT_SIZE 0x00020000
47 #define CONFIG_ENV_SECT_SIZE 0x00020000
51 #define CONFIG_ENV_SECT_SIZE 0x00040000
55 #define CONFIG_ENV_SECT_SIZE 0x00020000
59 #define CONFIG_ENV_SECT_SIZE 0x00040000
63 #define CONFIG_ENV_SECT_SIZE 0x00040000
67 #define CONFIG_ENV_SECT_SIZE 0x00020000
84 #define CONFIG_CONS_INDEX 0
87 #define CONFIG_SYS_SERIAL0 0x808C0000
[all …]
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| /OK3568_Linux_fs/kernel/drivers/staging/comedi/drivers/ |
| H A D | ke_counter.c | 26 * PCI BAR 0 Register I/O map
28 #define KE_RESET_REG(x) (0x00 + ((x) * 0x20))
29 #define KE_LATCH_REG(x) (0x00 + ((x) * 0x20))
30 #define KE_LSB_REG(x) (0x04 + ((x) * 0x20))
31 #define KE_MID_REG(x) (0x08 + ((x) * 0x20))
32 #define KE_MSB_REG(x) (0x0c + ((x) * 0x20))
33 #define KE_SIGN_REG(x) (0x10 + ((x) * 0x20))
34 #define KE_OSC_SEL_REG 0xf8
35 #define KE_OSC_SEL_CLK(x) (((x) & 0x3) << 0)
39 #define KE_DO_REG 0xfc
[all …]
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| /OK3568_Linux_fs/kernel/drivers/gpu/drm/amd/pm/powerplay/ |
| H A D | sislands_smc.h | 172 #define SISLANDS_SMC_STROBE_RATIO 0x0F
173 #define SISLANDS_SMC_STROBE_ENABLE 0x10
175 #define SISLANDS_SMC_MC_EDC_RD_FLAG 0x01
176 #define SISLANDS_SMC_MC_EDC_WR_FLAG 0x02
177 #define SISLANDS_SMC_MC_RTT_ENABLE 0x04
178 #define SISLANDS_SMC_MC_STUTTER_EN 0x08
179 #define SISLANDS_SMC_MC_PG_EN 0x10
194 #define SISLANDS_SMC_VOLTAGEMASK_VDDC 0
228 #define SI_SMC_SOFT_REGISTER_mclk_chg_timeout 0x0
229 #define SI_SMC_SOFT_REGISTER_delay_vreg 0xC
[all …]
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| /OK3568_Linux_fs/kernel/drivers/net/wireless/ath/ath9k/ |
| H A D | ar9003_phy.h | 23 #define AR_CHAN_BASE 0x9800
25 #define AR_PHY_TIMING1 (AR_CHAN_BASE + 0x0)
26 #define AR_PHY_TIMING2 (AR_CHAN_BASE + 0x4)
27 #define AR_PHY_TIMING3 (AR_CHAN_BASE + 0x8)
28 #define AR_PHY_TIMING4 (AR_CHAN_BASE + 0xc)
29 #define AR_PHY_TIMING5 (AR_CHAN_BASE + 0x10)
30 #define AR_PHY_TIMING6 (AR_CHAN_BASE + 0x14)
31 #define AR_PHY_TIMING11 (AR_CHAN_BASE + 0x18)
32 #define AR_PHY_SPUR_REG (AR_CHAN_BASE + 0x1c)
33 #define AR_PHY_RX_IQCAL_CORR_B0 (AR_CHAN_BASE + 0xdc)
[all …]
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| H A D | ar9003_eeprom.h | 22 #define AR9300_EEP_VER 0xD000
23 #define AR9300_EEP_VER_MINOR_MASK 0xFFF
24 #define AR9300_EEP_MINOR_VER_1 0x1
41 #define AR9300_EEPMISC_WOW 0x02
48 #define AR9300_PAPRD_RATE_MASK 0x01ffffff
49 #define AR9300_PAPRD_SCALE_1 0x0e000000
51 #define AR9300_PAPRD_SCALE_2 0x70000000
54 #define AR9300_EEP_ANTDIV_CONTROL_DEFAULT_VALUE 0xc9
63 #define AR9300_PWR_TABLE_OFFSET 0
78 #define AR9300_BASE_ADDR_4K 0xfff
[all …]
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| /OK3568_Linux_fs/kernel/arch/nds32/kernel/ |
| H A D | module.c | 13 GFP_KERNEL, PAGE_KERNEL, 0, NUMA_NO_NODE, in module_alloc()
14 __builtin_return_address(0)); in module_alloc()
26 return 0; in module_frob_arch_sections()
33 unsigned int tmp = 0, tmp2 = 0; in do_reloc16()
35 __asm__ __volatile__("\tlhi.bi\t%0, [%2], 0\n" in do_reloc16()
37 "\twsbh\t%0, %1\n" in do_reloc16()
38 "1:\n":"=r"(tmp):"0"(tmp), "r"(loc), "r"(swap) in do_reloc16()
51 "\twsbh\t%0, %1\n" in do_reloc16()
53 "\tshi.bi\t%0, [%2], 0\n":"=r"(tmp):"0"(tmp), in do_reloc16()
62 unsigned int tmp = 0, tmp2 = 0; in do_reloc32()
[all …]
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