1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-only
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * Au1300 media block power gating (VSS)
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * This is a stop-gap solution until I have the clock framework integration
6*4882a593Smuzhiyun * ready. This stuff here really must be handled transparently when clocks
7*4882a593Smuzhiyun * for various media blocks are enabled/disabled.
8*4882a593Smuzhiyun */
9*4882a593Smuzhiyun
10*4882a593Smuzhiyun #include <linux/export.h>
11*4882a593Smuzhiyun #include <linux/spinlock.h>
12*4882a593Smuzhiyun #include <asm/mach-au1x00/au1000.h>
13*4882a593Smuzhiyun
14*4882a593Smuzhiyun #define VSS_GATE 0x00 /* gate wait timers */
15*4882a593Smuzhiyun #define VSS_CLKRST 0x04 /* clock/block control */
16*4882a593Smuzhiyun #define VSS_FTR 0x08 /* footers */
17*4882a593Smuzhiyun
18*4882a593Smuzhiyun #define VSS_ADDR(blk) (KSEG1ADDR(AU1300_VSS_PHYS_ADDR) + (blk * 0x0c))
19*4882a593Smuzhiyun
20*4882a593Smuzhiyun static DEFINE_SPINLOCK(au1300_vss_lock);
21*4882a593Smuzhiyun
22*4882a593Smuzhiyun /* enable a block as outlined in the databook */
__enable_block(int block)23*4882a593Smuzhiyun static inline void __enable_block(int block)
24*4882a593Smuzhiyun {
25*4882a593Smuzhiyun void __iomem *base = (void __iomem *)VSS_ADDR(block);
26*4882a593Smuzhiyun
27*4882a593Smuzhiyun __raw_writel(3, base + VSS_CLKRST); /* enable clock, assert reset */
28*4882a593Smuzhiyun wmb();
29*4882a593Smuzhiyun
30*4882a593Smuzhiyun __raw_writel(0x01fffffe, base + VSS_GATE); /* maximum setup time */
31*4882a593Smuzhiyun wmb();
32*4882a593Smuzhiyun
33*4882a593Smuzhiyun /* enable footers in sequence */
34*4882a593Smuzhiyun __raw_writel(0x01, base + VSS_FTR);
35*4882a593Smuzhiyun wmb();
36*4882a593Smuzhiyun __raw_writel(0x03, base + VSS_FTR);
37*4882a593Smuzhiyun wmb();
38*4882a593Smuzhiyun __raw_writel(0x07, base + VSS_FTR);
39*4882a593Smuzhiyun wmb();
40*4882a593Smuzhiyun __raw_writel(0x0f, base + VSS_FTR);
41*4882a593Smuzhiyun wmb();
42*4882a593Smuzhiyun
43*4882a593Smuzhiyun __raw_writel(0x01ffffff, base + VSS_GATE); /* start FSM too */
44*4882a593Smuzhiyun wmb();
45*4882a593Smuzhiyun
46*4882a593Smuzhiyun __raw_writel(2, base + VSS_CLKRST); /* deassert reset */
47*4882a593Smuzhiyun wmb();
48*4882a593Smuzhiyun
49*4882a593Smuzhiyun __raw_writel(0x1f, base + VSS_FTR); /* enable isolation cells */
50*4882a593Smuzhiyun wmb();
51*4882a593Smuzhiyun }
52*4882a593Smuzhiyun
53*4882a593Smuzhiyun /* disable a block as outlined in the databook */
__disable_block(int block)54*4882a593Smuzhiyun static inline void __disable_block(int block)
55*4882a593Smuzhiyun {
56*4882a593Smuzhiyun void __iomem *base = (void __iomem *)VSS_ADDR(block);
57*4882a593Smuzhiyun
58*4882a593Smuzhiyun __raw_writel(0x0f, base + VSS_FTR); /* disable isolation cells */
59*4882a593Smuzhiyun wmb();
60*4882a593Smuzhiyun __raw_writel(0, base + VSS_GATE); /* disable FSM */
61*4882a593Smuzhiyun wmb();
62*4882a593Smuzhiyun __raw_writel(3, base + VSS_CLKRST); /* assert reset */
63*4882a593Smuzhiyun wmb();
64*4882a593Smuzhiyun __raw_writel(1, base + VSS_CLKRST); /* disable clock */
65*4882a593Smuzhiyun wmb();
66*4882a593Smuzhiyun __raw_writel(0, base + VSS_FTR); /* disable all footers */
67*4882a593Smuzhiyun wmb();
68*4882a593Smuzhiyun }
69*4882a593Smuzhiyun
au1300_vss_block_control(int block,int enable)70*4882a593Smuzhiyun void au1300_vss_block_control(int block, int enable)
71*4882a593Smuzhiyun {
72*4882a593Smuzhiyun unsigned long flags;
73*4882a593Smuzhiyun
74*4882a593Smuzhiyun if (alchemy_get_cputype() != ALCHEMY_CPU_AU1300)
75*4882a593Smuzhiyun return;
76*4882a593Smuzhiyun
77*4882a593Smuzhiyun /* only one block at a time */
78*4882a593Smuzhiyun spin_lock_irqsave(&au1300_vss_lock, flags);
79*4882a593Smuzhiyun if (enable)
80*4882a593Smuzhiyun __enable_block(block);
81*4882a593Smuzhiyun else
82*4882a593Smuzhiyun __disable_block(block);
83*4882a593Smuzhiyun spin_unlock_irqrestore(&au1300_vss_lock, flags);
84*4882a593Smuzhiyun }
85*4882a593Smuzhiyun EXPORT_SYMBOL_GPL(au1300_vss_block_control);
86