Lines Matching +full:0 +full:x01ffffff
125 #define NISLANDS_SMC_STROBE_RATIO 0x0F
126 #define NISLANDS_SMC_STROBE_ENABLE 0x10
128 #define NISLANDS_SMC_MC_EDC_RD_FLAG 0x01
129 #define NISLANDS_SMC_MC_EDC_WR_FLAG 0x02
130 #define NISLANDS_SMC_MC_RTT_ENABLE 0x04
131 #define NISLANDS_SMC_MC_STUTTER_EN 0x08
146 #define NISLANDS_SMC_VOLTAGEMASK_VDDC 0
180 #define NI_SMC_SOFT_REGISTERS_START 0x108
182 #define NI_SMC_SOFT_REGISTER_mclk_chg_timeout 0x0
183 #define NI_SMC_SOFT_REGISTER_delay_bbias 0xC
184 #define NI_SMC_SOFT_REGISTER_delay_vreg 0x10
185 #define NI_SMC_SOFT_REGISTER_delay_acpi 0x2C
186 #define NI_SMC_SOFT_REGISTER_seq_index 0x64
187 #define NI_SMC_SOFT_REGISTER_mvdd_chg_time 0x68
188 #define NI_SMC_SOFT_REGISTER_mclk_switch_lim 0x78
189 #define NI_SMC_SOFT_REGISTER_watermark_threshold 0x80
190 #define NI_SMC_SOFT_REGISTER_mc_block_delay 0x84
191 #define NI_SMC_SOFT_REGISTER_uvd_enabled 0x98
303 #define SMC_NISLANDS_SPLL_DIV_TABLE_FBDIV_MASK 0x01ffffff
304 #define SMC_NISLANDS_SPLL_DIV_TABLE_FBDIV_SHIFT 0
305 #define SMC_NISLANDS_SPLL_DIV_TABLE_PDIV_MASK 0xfe000000
307 #define SMC_NISLANDS_SPLL_DIV_TABLE_CLKV_MASK 0x000fffff
308 #define SMC_NISLANDS_SPLL_DIV_TABLE_CLKV_SHIFT 0
309 #define SMC_NISLANDS_SPLL_DIV_TABLE_CLKS_MASK 0xfff00000
314 #define NISLANDS_SMC_FIRMWARE_HEADER_LOCATION 0x100
316 #define NISLANDS_SMC_FIRMWARE_HEADER_version 0x0
317 #define NISLANDS_SMC_FIRMWARE_HEADER_flags 0x4
318 #define NISLANDS_SMC_FIRMWARE_HEADER_softRegisters 0x8
319 #define NISLANDS_SMC_FIRMWARE_HEADER_stateTable 0xC
320 #define NISLANDS_SMC_FIRMWARE_HEADER_fanTable 0x10
321 #define NISLANDS_SMC_FIRMWARE_HEADER_cacTable 0x14
322 #define NISLANDS_SMC_FIRMWARE_HEADER_mcRegisterTable 0x20
323 #define NISLANDS_SMC_FIRMWARE_HEADER_mcArbDramAutoRefreshTable 0x2C
324 #define NISLANDS_SMC_FIRMWARE_HEADER_spllTable 0x30