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/rk3399_ARM-atf/plat/rockchip/rk3576/drivers/secure/
H A Dsecure.h12 #define PMU0SGRF_SOC_CON(i) ((i) * 4) argument
15 #define PMU1SGRF_SOC_CON(i) ((i) * 4) argument
18 #define CCISGRF_SOC_CON(i) (0x20 + (i) * 4) argument
19 #define CCISGRF_DDR_HASH_CON(i) (0x40 + (i) * 4) argument
22 #define SYSSGRF_DDR_BANK_MSK(i) (0x04 + (i) * 4) argument
23 #define SYSSGRF_DDR_CH_MSK(i) (0x18 + (i) * 4) argument
24 #define SYSSGRF_SOC_CON(i) (0x20 + (i) * 4) argument
25 #define SYSSGRF_DMAC_CON(i) (0x80 + (i) * 4) argument
/rk3399_ARM-atf/plat/rockchip/rk3588/drivers/secure/
H A Dsecure.h11 #define DSU_SGRF_SOC_CON(i) ((i) * 4) argument
12 #define DSUSGRF_SOC_CON(i) ((i) * 4) argument
14 #define DSUSGRF_DDR_HASH_CON(i) (0x240 + (i) * 4) argument
21 #define SGRF_SOC_CON(i) ((i) * 4) argument
22 #define SGRF_FIREWALL_CON(i) (0x240 + (i) * 4) argument
26 #define FIREWALL_DDR_RGN(i) ((i) * 0x4) argument
28 #define FIREWALL_DDR_MST(i) (0x40 + (i) * 0x4) argument
32 #define FIREWALL_SYSMEM_RGN(i) ((i) * 0x4) argument
34 #define FIREWALL_SYSMEM_MST(i) (0x40 + (i) * 0x4) argument
38 #define FIREWALL_DSU_RGN(i) ((i) * 0x4) argument
[all …]
H A Dsecure.c17 uint32_t i; in secure_fw_master_init() local
62 int i; in dsu_fw_rgn_config() local
110 uint32_t i; in secure_region_init() local
148 uint32_t i; in sgrf_init() local
/rk3399_ARM-atf/plat/imx/imx9/common/
H A Dimx9_sys_sleep.c54 for (uint32_t i = 0U; i < GPIO_CTRL_REG_NUM; i++) { in gpio_save() local
66 for (uint32_t i = 0U; i < ctx->pin_num; i++) { in gpio_save() local
75 for (uint32_t i = 0U; i < 4U; i++) { in gpio_save() local
82 for (uint32_t i = 0U; i < 4U; i++) { in gpio_restore() local
86 for (uint32_t i = 0U; i < ctx->pin_num; i++) { in gpio_restore() local
90 for (uint32_t i = 4U; i < GPIO_CTRL_REG_NUM; i++) in gpio_restore() local
94 for (uint32_t i = 0U; i < 4U; i++) { in gpio_restore() local
150 for (uint32_t i = 0U; i < ARRAY_SIZE(per_hsk_cfg); i++) { in peripheral_qchannel_hsk() local
168 for (uint32_t i = 0U; i < IMR_NUM; i++) { in imx_set_sys_wakeup() local
204 for (uint32_t i = 0U; i < GPIO_NUM; i++) { in imx9_sys_sleep_prepare() local
[all …]
/rk3399_ARM-atf/plat/arm/common/fconf/
H A Dfconf_sdei_getter.c13 #define PRIVATE_EVENT_NUM(i) private_events[3 * (i)] argument
14 #define PRIVATE_EVENT_INTR(i) private_events[3 * (i) + 1] argument
15 #define PRIVATE_EVENT_FLAGS(i) private_events[3 * (i) + 2] argument
17 #define SHARED_EVENT_NUM(i) shared_events[3 * (i)] argument
18 #define SHARED_EVENT_INTR(i) shared_events[3 * (i) + 1] argument
19 #define SHARED_EVENT_FLAGS(i) shared_events[3 * (i) + 2] argument
25 uint32_t i; in fconf_populate_sdei_dyn_config() local
H A Dfconf_sec_intr_config.c13 #define G0_INTR_NUM(i) g0_intr_prop[3U * (i)] argument
14 #define G0_INTR_PRIORITY(i) g0_intr_prop[3U * (i) + 1] argument
15 #define G0_INTR_CONFIG(i) g0_intr_prop[3U * (i) + 2] argument
17 #define G1S_INTR_NUM(i) g1s_intr_prop[3U * (i)] argument
18 #define G1S_INTR_PRIORITY(i) g1s_intr_prop[3U * (i) + 1] argument
19 #define G1S_INTR_CONFIG(i) g1s_intr_prop[3U * (i) + 2] argument
103 for (uint32_t i = 0; i < g0_intr_count; i++) { in fconf_populate_sec_intr_config() local
116 for (uint32_t i = 0; i < g1s_intr_count; i++) { in fconf_populate_sec_intr_config() local
/rk3399_ARM-atf/plat/rockchip/rk3576/drivers/soc/
H A Dsoc.h32 #define CRU_PLLS_CON(pll_id, i) ((pll_id) * 0x20 + (i) * 0x4) argument
33 #define CRU_PLL_CON(i) ((i) * 0x4) argument
35 #define CRU_CLKSEL_CON(i) ((i) * 0x4 + 0x300) argument
37 #define CRU_CLKGATE_CON(i) ((i) * 0x4 + 0x800) argument
39 #define CRU_SOFTRST_CON(i) ((i) * 0x4 + 0xa00) argument
65 #define LCORE_CRU_CLKSEL_CON(i) ((i) * 0x4 + 0x300) argument
67 #define LCORE_CRU_CLKGATE_CON(i) ((i) * 0x4 + 0x800) argument
69 #define LCORE_CRU_SOFTRST_CON(i) ((i) * 0x4 + 0xa00) argument
74 #define BCORE_CRU_CLKSEL_CON(i) ((i) * 0x4 + 0x300) argument
76 #define BCORE_CRU_CLKGATE_CON(i) ((i) * 0x4 + 0x800) argument
[all …]
/rk3399_ARM-atf/plat/mediatek/mt8192/drivers/devapc/
H A Ddevapc.c2467 int d, i; in dump_infra_ao_apc() local
2509 int d, i; in dump_peri_ao_apc() local
2551 int d, i; in dump_peri_ao2_apc() local
2568 int d, i; in dump_peri_par_ao_apc() local
2588 uint32_t i; in set_infra_ao_apc() local
2657 uint32_t i; in set_peri_ao_apc() local
2734 uint32_t i; in set_peri_ao2_apc() local
2777 uint32_t i; in set_peri_par_ao_apc() local
/rk3399_ARM-atf/drivers/arm/gicv5/
H A Dgicv5_main.c78 for (int i = 0U; i < num_regs; i++) { in iwb_enable() local
83 for (int i = 0U; i < num_regs * 2; i++) { in iwb_enable() local
87 for (uint32_t i = 0U; i < config->num_wires; i++) { in iwb_enable() local
125 for (uint32_t i = spi_base; i < spi_base + spi_range; i++) { in irs_enable() local
129 for (uint32_t i = 0U; i < config->num_spis; i++) { in irs_enable() local
145 for (size_t i = 0U; i < plat_gicv5_driver_data.num_iwbs; i++) { in gicv5_driver_init() local
149 for (size_t i = 0U; i < plat_gicv5_driver_data.num_irss; i++) { in gicv5_driver_init() local
/rk3399_ARM-atf/plat/rockchip/rk3576/drivers/pmu/
H A Dpmu.h25 #define PMU0_DDR_RET_CON(i) (0x0020 + (i) * 4) argument
34 #define PMU1_DDR_PWR_CON(i) (PMU1_OFFSET + 0x0100 + (i) * 4) argument
35 #define PMU1_DDR_PWR_SFTCON(i) (PMU1_OFFSET + 0x0110 + (i) * 4) argument
36 #define PMU1_DDR_AXIPWR_CON(i) (PMU1_OFFSET + 0x0120 + (i) * 4) argument
37 #define PMU1_DDR_AXIPWR_SFTCON(i) (PMU1_OFFSET + 0x0130 + (i) * 4) argument
41 #define PMU1_CRU_PWR_CON(i) (PMU1_OFFSET + 0x0200 + (i) * 4) argument
42 #define PMU1_CRU_PWR_SFTCON(i) (PMU1_OFFSET + 0x0208 + (i) * 4) argument
44 #define PMU1_PLLPD_CON(i) (PMU1_OFFSET + 0x0220 + (i) * 4) argument
45 #define PMU1_PLLPD_SFTCON(i) (PMU1_OFFSET + 0x0228 + (i) * 4) argument
62 #define PMU2_DBG_PWR_CON(i) (PMU2_OFFSET + 0x001c + (i) * 4) argument
[all …]
/rk3399_ARM-atf/plat/rockchip/common/
H A Dplat_pm_helpers.c41 int i; in alloc_region_mem() local
92 int i, j; in rockchip_reg_rgn_save() local
112 int i, j; in rockchip_reg_rgn_restore() local
134 int i, j; in rockchip_reg_rgn_restore_reverse() local
150 int i; in rockchip_print_hex() local
176 uint32_t i; in rockchip_regs_dump() local
205 int i; in rockchip_dump_reg_rgns() local
/rk3399_ARM-atf/plat/imx/imx8ulp/
H A Dapd_context.c21 #define S400_MU_TRx(i) (S400_MU_BASE + 0x200 + (i) * 4) argument
22 #define S400_MU_RRx(i) (S400_MU_BASE + 0x280 + (i) * 4) argument
148 unsigned int i, j; in apd_io_pad_off() local
163 unsigned int i, j; in iomuxc_save() local
177 unsigned int i, j; in iomuxc_restore() local
189 unsigned int i, j; in gpio_save() local
216 unsigned int i, j; in gpio_restore() local
237 unsigned int i; in cgc1_save() local
257 unsigned int i; in cgc1_restore() local
367 unsigned int i; in lpav_ctx_save() local
[all …]
/rk3399_ARM-atf/plat/rockchip/rk3288/drivers/soc/
H A Dsoc.c145 uint32_t i = 0; in clk_gate_con_save() local
154 uint32_t i; in clk_gate_con_disable() local
162 uint32_t i; in clk_gate_con_restore() local
171 uint32_t i = 0; in clk_sel_con_save() local
180 uint32_t i, val; in clk_sel_con_restore() local
/rk3399_ARM-atf/plat/imx/imx8m/ddr/
H A Ddram.c100 unsigned int i, fsp_index; in get_mr_values() local
120 uint32_t i, offset; in save_rank_setting() local
144 unsigned int i; in dram_umctl2_init() local
159 unsigned int i; in dram_phy_init() local
219 unsigned int i; in dram_info_init() local
349 for (int i = 0; i < PLATFORM_CORE_COUNT; i++) { in dram_dvfs_handler() local
355 for (unsigned int i = 0; i < PLATFORM_CORE_COUNT; i++) { in dram_dvfs_handler() local
H A Dclock.c14 #define CCM_IP_CLK_ROOT_GEN_TAGET(i) (IMX_CCM_IP_BASE + 0x80 * (i) + 0x00) argument
15 #define CCM_IP_CLK_ROOT_GEN_TAGET_SET(i) (IMX_CCM_IP_BASE + 0x80 * (i) + 0x04) argument
16 #define CCM_IP_CLK_ROOT_GEN_TAGET_CLR(i) (IMX_CCM_IP_BASE + 0x80 * (i) + 0x08) argument
/rk3399_ARM-atf/plat/mediatek/drivers/apusys/mt8188/
H A Dapusys_rv_pwr_ctrl.h24 #define APU_MBOX(i) (((i) < MBOX_NUM) ? (APU_MBOX0 + MBOX_SIZE * (i)) : \ argument
26 #define APU_MBOX_FUNC_CFG(i) (APU_MBOX(i) + MBOX_FUNC_CFG) argument
27 #define APU_MBOX_DOMAIN_CFG(i) (APU_MBOX(i) + MBOX_DOMAIN_CFG) argument
/rk3399_ARM-atf/plat/rockchip/rk3588/drivers/pmu/
H A Dpmu.h19 #define PMU0_DDR_RET_CON(i) (0x0020 + (i) * 4) argument
30 #define PMU1_DDR_PWR_CON(i) (0x4020 + (i) * 4) argument
31 #define PMU1_DDR_PWR_SFTCON(i) (0x4030 + (i) * 4) argument
37 #define PMU1_PLLPD_CON(i) (0x4060 + (i) * 4) argument
38 #define PMU1_PLLPD_SFTCON(i) (0x4068 + (i) * 4) argument
45 #define PMU1_SYS_REG(i) (0x4100 + (i) * 4) argument
51 #define PMU2_CPU_AUTO_PWR_CON(i) (0x8010 + (i) * 4) argument
52 #define PMU2_CPU_PWR_SFTCON(i) (0x8030 + (i) * 4) argument
53 #define PMU2_CORE_PWR_CON(i) (0x8050 + (i) * 4) argument
54 #define PMU2_CORE_PWR_SFTCON(i) (0x8058 + (i) * 4) argument
[all …]
/rk3399_ARM-atf/drivers/arm/gic/v3/
H A Dgic600_multichip.c29 unsigned int i; in gic600_multichip_gicd_base_for_spi() local
205 unsigned int i, spi_id_min, spi_id_max, blocks_of_32; in gic600_multichip_validate_data() local
250 unsigned int i, spi_id_min, spi_id_max, blocks_of_32; in gic700_multichip_validate_data() local
335 unsigned int i, j; in gic600_multichip_lca_init() local
359 unsigned int i; in gic600_multichip_init() local
/rk3399_ARM-atf/plat/nuvoton/npcm845x/
H A Dnpcm845x_psci.c168 for (size_t i = 0; (uint64_t)i <= PLAT_MAX_PWR_LVL; i++) { in npcm845x_pwr_domain_suspend() local
188 for (size_t i = 0; (uint64_t)i <= PLAT_MAX_PWR_LVL; i++) { in npcm845x_pwr_domain_on_finish() local
210 for (size_t i = 0; (uint64_t)i <= PLAT_MAX_PWR_LVL; i++) { in npcm845x_pwr_domain_suspend_finish() local
259 int i; in npcm845x_validate_power_state() local
302 unsigned int i; in npcm845x_get_sys_suspend_power_state() local
367 for (size_t i = 0; (uint64_t)i <= PLAT_MAX_PWR_LVL; i++) { in npcm845x_pwr_domain_off() local
/rk3399_ARM-atf/plat/imx/common/
H A Dimx_aips.c15 int i; in imx_aips_set_default_access() local
48 int i; in imx_aips_init() local
H A Dimx7_clock.c11 unsigned int i; in imx7_clock_uart_init() local
19 unsigned int i; in imx7_clock_wdog_init() local
/rk3399_ARM-atf/plat/rockchip/px30/drivers/soc/
H A Dsoc.c48 uint32_t i, j; in clk_gate_con_save() local
61 uint32_t i, j; in clk_gate_con_restore() local
75 uint32_t i; in clk_gate_con_disable() local
/rk3399_ARM-atf/plat/rockchip/px30/drivers/secure/
H A Dsecure.h13 #define SGRF_SOC_CON(i) ((i) * 0x4) argument
14 #define SGRF_DMAC_CON(i) (0x30 + (i) * 0x4) argument
28 #define FIREWALL_DDR_FW_DDR_RGN(i) ((i) * 0x4) argument
29 #define FIREWALL_DDR_FW_DDR_MST(i) (0x20 + (i) * 0x4) argument
/rk3399_ARM-atf/lib/utils/
H A Dmem_region.c33 size_t i; in clear_mem_regions() local
70 for (unsigned int i = 0U; i < nregions; i++) { in clear_map_dyn_mem_regions() local
119 size_t i; in mem_region_in_array_chk() local
/rk3399_ARM-atf/plat/renesas/common/
H A Dbl2_secure_setting.c351 uint32_t i; in lifec_security_setting() local
360 uint32_t i; in axi_security_setting() local
369 uint32_t i; in bl2_ram_security_setting_finish() local

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