1 /* 2 * (C) Copyright 2017 3 * Vikas Manocha, <vikas.manocha@st.com> 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8 #include <common.h> 9 #include <clk.h> 10 #include <dm.h> 11 #include <ram.h> 12 #include <asm/io.h> 13 #include <asm/arch/stm32.h> 14 15 DECLARE_GLOBAL_DATA_PTR; 16 17 struct stm32_fmc_regs { 18 u32 sdcr1; /* Control register 1 */ 19 u32 sdcr2; /* Control register 2 */ 20 u32 sdtr1; /* Timing register 1 */ 21 u32 sdtr2; /* Timing register 2 */ 22 u32 sdcmr; /* Mode register */ 23 u32 sdrtr; /* Refresh timing register */ 24 u32 sdsr; /* Status register */ 25 }; 26 27 /* 28 * FMC registers base 29 */ 30 #define STM32_SDRAM_FMC ((struct stm32_fmc_regs *)SDRAM_FMC_BASE) 31 32 /* Control register SDCR */ 33 #define FMC_SDCR_RPIPE_SHIFT 13 /* RPIPE bit shift */ 34 #define FMC_SDCR_RBURST_SHIFT 12 /* RBURST bit shift */ 35 #define FMC_SDCR_SDCLK_SHIFT 10 /* SDRAM clock divisor shift */ 36 #define FMC_SDCR_WP_SHIFT 9 /* Write protection shift */ 37 #define FMC_SDCR_CAS_SHIFT 7 /* CAS latency shift */ 38 #define FMC_SDCR_NB_SHIFT 6 /* Number of banks shift */ 39 #define FMC_SDCR_MWID_SHIFT 4 /* Memory width shift */ 40 #define FMC_SDCR_NR_SHIFT 2 /* Number of row address bits shift */ 41 #define FMC_SDCR_NC_SHIFT 0 /* Number of col address bits shift */ 42 43 /* Timings register SDTR */ 44 #define FMC_SDTR_TMRD_SHIFT 0 /* Load mode register to active */ 45 #define FMC_SDTR_TXSR_SHIFT 4 /* Exit self-refresh time */ 46 #define FMC_SDTR_TRAS_SHIFT 8 /* Self-refresh time */ 47 #define FMC_SDTR_TRC_SHIFT 12 /* Row cycle delay */ 48 #define FMC_SDTR_TWR_SHIFT 16 /* Recovery delay */ 49 #define FMC_SDTR_TRP_SHIFT 20 /* Row precharge delay */ 50 #define FMC_SDTR_TRCD_SHIFT 24 /* Row-to-column delay */ 51 52 #define FMC_SDCMR_NRFS_SHIFT 5 53 54 #define FMC_SDCMR_MODE_NORMAL 0 55 #define FMC_SDCMR_MODE_START_CLOCK 1 56 #define FMC_SDCMR_MODE_PRECHARGE 2 57 #define FMC_SDCMR_MODE_AUTOREFRESH 3 58 #define FMC_SDCMR_MODE_WRITE_MODE 4 59 #define FMC_SDCMR_MODE_SELFREFRESH 5 60 #define FMC_SDCMR_MODE_POWERDOWN 6 61 62 #define FMC_SDCMR_BANK_1 BIT(4) 63 #define FMC_SDCMR_BANK_2 BIT(3) 64 65 #define FMC_SDCMR_MODE_REGISTER_SHIFT 9 66 67 #define FMC_SDSR_BUSY BIT(5) 68 69 #define FMC_BUSY_WAIT() do { \ 70 __asm__ __volatile__ ("dsb" : : : "memory"); \ 71 while (STM32_SDRAM_FMC->sdsr & FMC_SDSR_BUSY) \ 72 ; \ 73 } while (0) 74 75 struct stm32_sdram_control { 76 u8 no_columns; 77 u8 no_rows; 78 u8 memory_width; 79 u8 no_banks; 80 u8 cas_latency; 81 u8 sdclk; 82 u8 rd_burst; 83 u8 rd_pipe_delay; 84 }; 85 86 struct stm32_sdram_timing { 87 u8 tmrd; 88 u8 txsr; 89 u8 tras; 90 u8 trc; 91 u8 trp; 92 u8 twr; 93 u8 trcd; 94 }; 95 struct stm32_sdram_params { 96 u8 no_sdram_banks; 97 struct stm32_sdram_control sdram_control; 98 struct stm32_sdram_timing sdram_timing; 99 u32 sdram_ref_count; 100 }; 101 102 #define SDRAM_MODE_BL_SHIFT 0 103 #define SDRAM_MODE_CAS_SHIFT 4 104 #define SDRAM_MODE_BL 0 105 106 int stm32_sdram_init(struct udevice *dev) 107 { 108 struct stm32_sdram_params *params = dev_get_platdata(dev); 109 110 writel(params->sdram_control.sdclk << FMC_SDCR_SDCLK_SHIFT 111 | params->sdram_control.cas_latency << FMC_SDCR_CAS_SHIFT 112 | params->sdram_control.no_banks << FMC_SDCR_NB_SHIFT 113 | params->sdram_control.memory_width << FMC_SDCR_MWID_SHIFT 114 | params->sdram_control.no_rows << FMC_SDCR_NR_SHIFT 115 | params->sdram_control.no_columns << FMC_SDCR_NC_SHIFT 116 | params->sdram_control.rd_pipe_delay << FMC_SDCR_RPIPE_SHIFT 117 | params->sdram_control.rd_burst << FMC_SDCR_RBURST_SHIFT, 118 &STM32_SDRAM_FMC->sdcr1); 119 120 writel(params->sdram_timing.trcd << FMC_SDTR_TRCD_SHIFT 121 | params->sdram_timing.trp << FMC_SDTR_TRP_SHIFT 122 | params->sdram_timing.twr << FMC_SDTR_TWR_SHIFT 123 | params->sdram_timing.trc << FMC_SDTR_TRC_SHIFT 124 | params->sdram_timing.tras << FMC_SDTR_TRAS_SHIFT 125 | params->sdram_timing.txsr << FMC_SDTR_TXSR_SHIFT 126 | params->sdram_timing.tmrd << FMC_SDTR_TMRD_SHIFT, 127 &STM32_SDRAM_FMC->sdtr1); 128 129 writel(FMC_SDCMR_BANK_1 | FMC_SDCMR_MODE_START_CLOCK, 130 &STM32_SDRAM_FMC->sdcmr); 131 udelay(200); /* 200 us delay, page 10, "Power-Up" */ 132 FMC_BUSY_WAIT(); 133 134 writel(FMC_SDCMR_BANK_1 | FMC_SDCMR_MODE_PRECHARGE, 135 &STM32_SDRAM_FMC->sdcmr); 136 udelay(100); 137 FMC_BUSY_WAIT(); 138 139 writel((FMC_SDCMR_BANK_1 | FMC_SDCMR_MODE_AUTOREFRESH 140 | 7 << FMC_SDCMR_NRFS_SHIFT), &STM32_SDRAM_FMC->sdcmr); 141 udelay(100); 142 FMC_BUSY_WAIT(); 143 144 writel(FMC_SDCMR_BANK_1 | (SDRAM_MODE_BL << SDRAM_MODE_BL_SHIFT 145 | params->sdram_control.cas_latency << SDRAM_MODE_CAS_SHIFT) 146 << FMC_SDCMR_MODE_REGISTER_SHIFT | FMC_SDCMR_MODE_WRITE_MODE, 147 &STM32_SDRAM_FMC->sdcmr); 148 udelay(100); 149 FMC_BUSY_WAIT(); 150 151 writel(FMC_SDCMR_BANK_1 | FMC_SDCMR_MODE_NORMAL, 152 &STM32_SDRAM_FMC->sdcmr); 153 FMC_BUSY_WAIT(); 154 155 /* Refresh timer */ 156 writel((params->sdram_ref_count) << 1, &STM32_SDRAM_FMC->sdrtr); 157 158 return 0; 159 } 160 161 static int stm32_fmc_ofdata_to_platdata(struct udevice *dev) 162 { 163 int ret; 164 int node = dev_of_offset(dev); 165 const void *blob = gd->fdt_blob; 166 struct stm32_sdram_params *params = dev_get_platdata(dev); 167 168 params->no_sdram_banks = fdtdec_get_uint(blob, node, "mr-nbanks", 1); 169 debug("%s, no of banks = %d\n", __func__, params->no_sdram_banks); 170 171 fdt_for_each_subnode(node, blob, node) { 172 ret = fdtdec_get_byte_array(blob, node, "st,sdram-control", 173 (u8 *)¶ms->sdram_control, 174 sizeof(params->sdram_control)); 175 if (ret) 176 return ret; 177 ret = fdtdec_get_byte_array(blob, node, "st,sdram-timing", 178 (u8 *)¶ms->sdram_timing, 179 sizeof(params->sdram_timing)); 180 if (ret) 181 return ret; 182 183 params->sdram_ref_count = fdtdec_get_int(blob, node, 184 "st,sdram-refcount", 8196); 185 } 186 187 return 0; 188 } 189 190 static int stm32_fmc_probe(struct udevice *dev) 191 { 192 int ret; 193 #ifdef CONFIG_CLK 194 struct clk clk; 195 196 ret = clk_get_by_index(dev, 0, &clk); 197 if (ret < 0) 198 return ret; 199 200 ret = clk_enable(&clk); 201 202 if (ret) { 203 dev_err(dev, "failed to enable clock\n"); 204 return ret; 205 } 206 #endif 207 ret = stm32_sdram_init(dev); 208 if (ret) 209 return ret; 210 211 return 0; 212 } 213 214 static int stm32_fmc_get_info(struct udevice *dev, struct ram_info *info) 215 { 216 return 0; 217 } 218 219 static struct ram_ops stm32_fmc_ops = { 220 .get_info = stm32_fmc_get_info, 221 }; 222 223 static const struct udevice_id stm32_fmc_ids[] = { 224 { .compatible = "st,stm32-fmc" }, 225 { } 226 }; 227 228 U_BOOT_DRIVER(stm32_fmc) = { 229 .name = "stm32_fmc", 230 .id = UCLASS_RAM, 231 .of_match = stm32_fmc_ids, 232 .ops = &stm32_fmc_ops, 233 .ofdata_to_platdata = stm32_fmc_ofdata_to_platdata, 234 .probe = stm32_fmc_probe, 235 .platdata_auto_alloc_size = sizeof(struct stm32_sdram_params), 236 }; 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