1 /* 2 * (C) Copyright 2017 3 * Vikas Manocha, <vikas.manocha@st.com> 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8 #include <common.h> 9 #include <clk.h> 10 #include <dm.h> 11 #include <ram.h> 12 #include <asm/io.h> 13 14 DECLARE_GLOBAL_DATA_PTR; 15 16 struct stm32_fmc_regs { 17 /* 0x0 */ 18 u32 bcr1; /* NOR/PSRAM Chip select control register 1 */ 19 u32 btr1; /* SRAM/NOR-Flash Chip select timing register 1 */ 20 u32 bcr2; /* NOR/PSRAM Chip select Control register 2 */ 21 u32 btr2; /* SRAM/NOR-Flash Chip select timing register 2 */ 22 u32 bcr3; /* NOR/PSRAMChip select Control register 3 */ 23 u32 btr3; /* SRAM/NOR-Flash Chip select timing register 3 */ 24 u32 bcr4; /* NOR/PSRAM Chip select Control register 4 */ 25 u32 btr4; /* SRAM/NOR-Flash Chip select timing register 4 */ 26 u32 reserved1[24]; 27 28 /* 0x80 */ 29 u32 pcr; /* NAND Flash control register */ 30 u32 sr; /* FIFO status and interrupt register */ 31 u32 pmem; /* Common memory space timing register */ 32 u32 patt; /* Attribute memory space timing registers */ 33 u32 reserved2[1]; 34 u32 eccr; /* ECC result registers */ 35 u32 reserved3[27]; 36 37 /* 0x104 */ 38 u32 bwtr1; /* SRAM/NOR-Flash write timing register 1 */ 39 u32 reserved4[1]; 40 u32 bwtr2; /* SRAM/NOR-Flash write timing register 2 */ 41 u32 reserved5[1]; 42 u32 bwtr3; /* SRAM/NOR-Flash write timing register 3 */ 43 u32 reserved6[1]; 44 u32 bwtr4; /* SRAM/NOR-Flash write timing register 4 */ 45 u32 reserved7[8]; 46 47 /* 0x140 */ 48 u32 sdcr1; /* SDRAM Control register 1 */ 49 u32 sdcr2; /* SDRAM Control register 2 */ 50 u32 sdtr1; /* SDRAM Timing register 1 */ 51 u32 sdtr2; /* SDRAM Timing register 2 */ 52 u32 sdcmr; /* SDRAM Mode register */ 53 u32 sdrtr; /* SDRAM Refresh timing register */ 54 u32 sdsr; /* SDRAM Status register */ 55 }; 56 57 /* Control register SDCR */ 58 #define FMC_SDCR_RPIPE_SHIFT 13 /* RPIPE bit shift */ 59 #define FMC_SDCR_RBURST_SHIFT 12 /* RBURST bit shift */ 60 #define FMC_SDCR_SDCLK_SHIFT 10 /* SDRAM clock divisor shift */ 61 #define FMC_SDCR_WP_SHIFT 9 /* Write protection shift */ 62 #define FMC_SDCR_CAS_SHIFT 7 /* CAS latency shift */ 63 #define FMC_SDCR_NB_SHIFT 6 /* Number of banks shift */ 64 #define FMC_SDCR_MWID_SHIFT 4 /* Memory width shift */ 65 #define FMC_SDCR_NR_SHIFT 2 /* Number of row address bits shift */ 66 #define FMC_SDCR_NC_SHIFT 0 /* Number of col address bits shift */ 67 68 /* Timings register SDTR */ 69 #define FMC_SDTR_TMRD_SHIFT 0 /* Load mode register to active */ 70 #define FMC_SDTR_TXSR_SHIFT 4 /* Exit self-refresh time */ 71 #define FMC_SDTR_TRAS_SHIFT 8 /* Self-refresh time */ 72 #define FMC_SDTR_TRC_SHIFT 12 /* Row cycle delay */ 73 #define FMC_SDTR_TWR_SHIFT 16 /* Recovery delay */ 74 #define FMC_SDTR_TRP_SHIFT 20 /* Row precharge delay */ 75 #define FMC_SDTR_TRCD_SHIFT 24 /* Row-to-column delay */ 76 77 #define FMC_SDCMR_NRFS_SHIFT 5 78 79 #define FMC_SDCMR_MODE_NORMAL 0 80 #define FMC_SDCMR_MODE_START_CLOCK 1 81 #define FMC_SDCMR_MODE_PRECHARGE 2 82 #define FMC_SDCMR_MODE_AUTOREFRESH 3 83 #define FMC_SDCMR_MODE_WRITE_MODE 4 84 #define FMC_SDCMR_MODE_SELFREFRESH 5 85 #define FMC_SDCMR_MODE_POWERDOWN 6 86 87 #define FMC_SDCMR_BANK_1 BIT(4) 88 #define FMC_SDCMR_BANK_2 BIT(3) 89 90 #define FMC_SDCMR_MODE_REGISTER_SHIFT 9 91 92 #define FMC_SDSR_BUSY BIT(5) 93 94 #define FMC_BUSY_WAIT(regs) do { \ 95 __asm__ __volatile__ ("dsb" : : : "memory"); \ 96 while (regs->sdsr & FMC_SDSR_BUSY) \ 97 ; \ 98 } while (0) 99 100 struct stm32_sdram_control { 101 u8 no_columns; 102 u8 no_rows; 103 u8 memory_width; 104 u8 no_banks; 105 u8 cas_latency; 106 u8 sdclk; 107 u8 rd_burst; 108 u8 rd_pipe_delay; 109 }; 110 111 struct stm32_sdram_timing { 112 u8 tmrd; 113 u8 txsr; 114 u8 tras; 115 u8 trc; 116 u8 trp; 117 u8 twr; 118 u8 trcd; 119 }; 120 struct stm32_sdram_params { 121 struct stm32_fmc_regs *base; 122 u8 no_sdram_banks; 123 struct stm32_sdram_control sdram_control; 124 struct stm32_sdram_timing sdram_timing; 125 u32 sdram_ref_count; 126 }; 127 128 #define SDRAM_MODE_BL_SHIFT 0 129 #define SDRAM_MODE_CAS_SHIFT 4 130 #define SDRAM_MODE_BL 0 131 132 int stm32_sdram_init(struct udevice *dev) 133 { 134 struct stm32_sdram_params *params = dev_get_platdata(dev); 135 struct stm32_fmc_regs *regs = params->base; 136 137 writel(params->sdram_control.sdclk << FMC_SDCR_SDCLK_SHIFT 138 | params->sdram_control.cas_latency << FMC_SDCR_CAS_SHIFT 139 | params->sdram_control.no_banks << FMC_SDCR_NB_SHIFT 140 | params->sdram_control.memory_width << FMC_SDCR_MWID_SHIFT 141 | params->sdram_control.no_rows << FMC_SDCR_NR_SHIFT 142 | params->sdram_control.no_columns << FMC_SDCR_NC_SHIFT 143 | params->sdram_control.rd_pipe_delay << FMC_SDCR_RPIPE_SHIFT 144 | params->sdram_control.rd_burst << FMC_SDCR_RBURST_SHIFT, 145 ®s->sdcr1); 146 147 writel(params->sdram_timing.trcd << FMC_SDTR_TRCD_SHIFT 148 | params->sdram_timing.trp << FMC_SDTR_TRP_SHIFT 149 | params->sdram_timing.twr << FMC_SDTR_TWR_SHIFT 150 | params->sdram_timing.trc << FMC_SDTR_TRC_SHIFT 151 | params->sdram_timing.tras << FMC_SDTR_TRAS_SHIFT 152 | params->sdram_timing.txsr << FMC_SDTR_TXSR_SHIFT 153 | params->sdram_timing.tmrd << FMC_SDTR_TMRD_SHIFT, 154 ®s->sdtr1); 155 156 writel(FMC_SDCMR_BANK_1 | FMC_SDCMR_MODE_START_CLOCK, 157 ®s->sdcmr); 158 udelay(200); /* 200 us delay, page 10, "Power-Up" */ 159 FMC_BUSY_WAIT(regs); 160 161 writel(FMC_SDCMR_BANK_1 | FMC_SDCMR_MODE_PRECHARGE, 162 ®s->sdcmr); 163 udelay(100); 164 FMC_BUSY_WAIT(regs); 165 166 writel((FMC_SDCMR_BANK_1 | FMC_SDCMR_MODE_AUTOREFRESH 167 | 7 << FMC_SDCMR_NRFS_SHIFT), ®s->sdcmr); 168 udelay(100); 169 FMC_BUSY_WAIT(regs); 170 171 writel(FMC_SDCMR_BANK_1 | (SDRAM_MODE_BL << SDRAM_MODE_BL_SHIFT 172 | params->sdram_control.cas_latency << SDRAM_MODE_CAS_SHIFT) 173 << FMC_SDCMR_MODE_REGISTER_SHIFT | FMC_SDCMR_MODE_WRITE_MODE, 174 ®s->sdcmr); 175 udelay(100); 176 FMC_BUSY_WAIT(regs); 177 178 writel(FMC_SDCMR_BANK_1 | FMC_SDCMR_MODE_NORMAL, 179 ®s->sdcmr); 180 FMC_BUSY_WAIT(regs); 181 182 /* Refresh timer */ 183 writel((params->sdram_ref_count) << 1, ®s->sdrtr); 184 185 return 0; 186 } 187 188 static int stm32_fmc_ofdata_to_platdata(struct udevice *dev) 189 { 190 int ret; 191 int node = dev_of_offset(dev); 192 const void *blob = gd->fdt_blob; 193 struct stm32_sdram_params *params = dev_get_platdata(dev); 194 195 params->no_sdram_banks = fdtdec_get_uint(blob, node, "mr-nbanks", 1); 196 debug("%s, no of banks = %d\n", __func__, params->no_sdram_banks); 197 198 fdt_for_each_subnode(node, blob, node) { 199 ret = fdtdec_get_byte_array(blob, node, "st,sdram-control", 200 (u8 *)¶ms->sdram_control, 201 sizeof(params->sdram_control)); 202 if (ret) 203 return ret; 204 ret = fdtdec_get_byte_array(blob, node, "st,sdram-timing", 205 (u8 *)¶ms->sdram_timing, 206 sizeof(params->sdram_timing)); 207 if (ret) 208 return ret; 209 210 params->sdram_ref_count = fdtdec_get_int(blob, node, 211 "st,sdram-refcount", 8196); 212 } 213 214 return 0; 215 } 216 217 static int stm32_fmc_probe(struct udevice *dev) 218 { 219 struct stm32_sdram_params *params = dev_get_platdata(dev); 220 int ret; 221 fdt_addr_t addr; 222 223 addr = dev_read_addr(dev); 224 if (addr == FDT_ADDR_T_NONE) 225 return -EINVAL; 226 227 params->base = (struct stm32_fmc_regs *)addr; 228 229 #ifdef CONFIG_CLK 230 struct clk clk; 231 232 ret = clk_get_by_index(dev, 0, &clk); 233 if (ret < 0) 234 return ret; 235 236 ret = clk_enable(&clk); 237 238 if (ret) { 239 dev_err(dev, "failed to enable clock\n"); 240 return ret; 241 } 242 #endif 243 ret = stm32_sdram_init(dev); 244 if (ret) 245 return ret; 246 247 return 0; 248 } 249 250 static int stm32_fmc_get_info(struct udevice *dev, struct ram_info *info) 251 { 252 return 0; 253 } 254 255 static struct ram_ops stm32_fmc_ops = { 256 .get_info = stm32_fmc_get_info, 257 }; 258 259 static const struct udevice_id stm32_fmc_ids[] = { 260 { .compatible = "st,stm32-fmc" }, 261 { } 262 }; 263 264 U_BOOT_DRIVER(stm32_fmc) = { 265 .name = "stm32_fmc", 266 .id = UCLASS_RAM, 267 .of_match = stm32_fmc_ids, 268 .ops = &stm32_fmc_ops, 269 .ofdata_to_platdata = stm32_fmc_ofdata_to_platdata, 270 .probe = stm32_fmc_probe, 271 .platdata_auto_alloc_size = sizeof(struct stm32_sdram_params), 272 }; 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