1 /* 2 * (C) Copyright 2017 3 * Vikas Manocha, <vikas.manocha@st.com> 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8 #include <common.h> 9 #include <clk.h> 10 #include <dm.h> 11 #include <ram.h> 12 #include <asm/io.h> 13 14 DECLARE_GLOBAL_DATA_PTR; 15 16 struct stm32_fmc_regs { 17 /* 0x0 */ 18 u32 bcr1; /* NOR/PSRAM Chip select control register 1 */ 19 u32 btr1; /* SRAM/NOR-Flash Chip select timing register 1 */ 20 u32 bcr2; /* NOR/PSRAM Chip select Control register 2 */ 21 u32 btr2; /* SRAM/NOR-Flash Chip select timing register 2 */ 22 u32 bcr3; /* NOR/PSRAMChip select Control register 3 */ 23 u32 btr3; /* SRAM/NOR-Flash Chip select timing register 3 */ 24 u32 bcr4; /* NOR/PSRAM Chip select Control register 4 */ 25 u32 btr4; /* SRAM/NOR-Flash Chip select timing register 4 */ 26 u32 reserved1[24]; 27 28 /* 0x80 */ 29 u32 pcr; /* NAND Flash control register */ 30 u32 sr; /* FIFO status and interrupt register */ 31 u32 pmem; /* Common memory space timing register */ 32 u32 patt; /* Attribute memory space timing registers */ 33 u32 reserved2[1]; 34 u32 eccr; /* ECC result registers */ 35 u32 reserved3[27]; 36 37 /* 0x104 */ 38 u32 bwtr1; /* SRAM/NOR-Flash write timing register 1 */ 39 u32 reserved4[1]; 40 u32 bwtr2; /* SRAM/NOR-Flash write timing register 2 */ 41 u32 reserved5[1]; 42 u32 bwtr3; /* SRAM/NOR-Flash write timing register 3 */ 43 u32 reserved6[1]; 44 u32 bwtr4; /* SRAM/NOR-Flash write timing register 4 */ 45 u32 reserved7[8]; 46 47 /* 0x140 */ 48 u32 sdcr1; /* SDRAM Control register 1 */ 49 u32 sdcr2; /* SDRAM Control register 2 */ 50 u32 sdtr1; /* SDRAM Timing register 1 */ 51 u32 sdtr2; /* SDRAM Timing register 2 */ 52 u32 sdcmr; /* SDRAM Mode register */ 53 u32 sdrtr; /* SDRAM Refresh timing register */ 54 u32 sdsr; /* SDRAM Status register */ 55 }; 56 57 /* Control register SDCR */ 58 #define FMC_SDCR_RPIPE_SHIFT 13 /* RPIPE bit shift */ 59 #define FMC_SDCR_RBURST_SHIFT 12 /* RBURST bit shift */ 60 #define FMC_SDCR_SDCLK_SHIFT 10 /* SDRAM clock divisor shift */ 61 #define FMC_SDCR_WP_SHIFT 9 /* Write protection shift */ 62 #define FMC_SDCR_CAS_SHIFT 7 /* CAS latency shift */ 63 #define FMC_SDCR_NB_SHIFT 6 /* Number of banks shift */ 64 #define FMC_SDCR_MWID_SHIFT 4 /* Memory width shift */ 65 #define FMC_SDCR_NR_SHIFT 2 /* Number of row address bits shift */ 66 #define FMC_SDCR_NC_SHIFT 0 /* Number of col address bits shift */ 67 68 /* Timings register SDTR */ 69 #define FMC_SDTR_TMRD_SHIFT 0 /* Load mode register to active */ 70 #define FMC_SDTR_TXSR_SHIFT 4 /* Exit self-refresh time */ 71 #define FMC_SDTR_TRAS_SHIFT 8 /* Self-refresh time */ 72 #define FMC_SDTR_TRC_SHIFT 12 /* Row cycle delay */ 73 #define FMC_SDTR_TWR_SHIFT 16 /* Recovery delay */ 74 #define FMC_SDTR_TRP_SHIFT 20 /* Row precharge delay */ 75 #define FMC_SDTR_TRCD_SHIFT 24 /* Row-to-column delay */ 76 77 #define FMC_SDCMR_NRFS_SHIFT 5 78 79 #define FMC_SDCMR_MODE_NORMAL 0 80 #define FMC_SDCMR_MODE_START_CLOCK 1 81 #define FMC_SDCMR_MODE_PRECHARGE 2 82 #define FMC_SDCMR_MODE_AUTOREFRESH 3 83 #define FMC_SDCMR_MODE_WRITE_MODE 4 84 #define FMC_SDCMR_MODE_SELFREFRESH 5 85 #define FMC_SDCMR_MODE_POWERDOWN 6 86 87 #define FMC_SDCMR_BANK_1 BIT(4) 88 #define FMC_SDCMR_BANK_2 BIT(3) 89 90 #define FMC_SDCMR_MODE_REGISTER_SHIFT 9 91 92 #define FMC_SDSR_BUSY BIT(5) 93 94 #define FMC_BUSY_WAIT(regs) do { \ 95 __asm__ __volatile__ ("dsb" : : : "memory"); \ 96 while (regs->sdsr & FMC_SDSR_BUSY) \ 97 ; \ 98 } while (0) 99 100 struct stm32_sdram_control { 101 u8 no_columns; 102 u8 no_rows; 103 u8 memory_width; 104 u8 no_banks; 105 u8 cas_latency; 106 u8 sdclk; 107 u8 rd_burst; 108 u8 rd_pipe_delay; 109 }; 110 111 struct stm32_sdram_timing { 112 u8 tmrd; 113 u8 txsr; 114 u8 tras; 115 u8 trc; 116 u8 trp; 117 u8 twr; 118 u8 trcd; 119 }; 120 enum stm32_fmc_bank { 121 SDRAM_BANK1, 122 SDRAM_BANK2, 123 MAX_SDRAM_BANK, 124 }; 125 126 struct bank_params { 127 struct stm32_sdram_control *sdram_control; 128 struct stm32_sdram_timing *sdram_timing; 129 u32 sdram_ref_count; 130 enum stm32_fmc_bank target_bank; 131 }; 132 133 struct stm32_sdram_params { 134 struct stm32_fmc_regs *base; 135 u8 no_sdram_banks; 136 struct bank_params bank_params[MAX_SDRAM_BANK]; 137 }; 138 139 #define SDRAM_MODE_BL_SHIFT 0 140 #define SDRAM_MODE_CAS_SHIFT 4 141 #define SDRAM_MODE_BL 0 142 143 int stm32_sdram_init(struct udevice *dev) 144 { 145 struct stm32_sdram_params *params = dev_get_platdata(dev); 146 struct stm32_sdram_control *control; 147 struct stm32_sdram_timing *timing; 148 struct stm32_fmc_regs *regs = params->base; 149 enum stm32_fmc_bank target_bank; 150 u32 ctb; /* SDCMR register: Command Target Bank */ 151 u32 ref_count; 152 u8 i; 153 154 for (i = 0; i < params->no_sdram_banks; i++) { 155 control = params->bank_params[i].sdram_control; 156 timing = params->bank_params[i].sdram_timing; 157 target_bank = params->bank_params[i].target_bank; 158 ref_count = params->bank_params[i].sdram_ref_count; 159 160 writel(control->sdclk << FMC_SDCR_SDCLK_SHIFT 161 | control->cas_latency << FMC_SDCR_CAS_SHIFT 162 | control->no_banks << FMC_SDCR_NB_SHIFT 163 | control->memory_width << FMC_SDCR_MWID_SHIFT 164 | control->no_rows << FMC_SDCR_NR_SHIFT 165 | control->no_columns << FMC_SDCR_NC_SHIFT 166 | control->rd_pipe_delay << FMC_SDCR_RPIPE_SHIFT 167 | control->rd_burst << FMC_SDCR_RBURST_SHIFT, 168 ®s->sdcr1); 169 170 if (target_bank == SDRAM_BANK2) 171 writel(control->cas_latency << FMC_SDCR_CAS_SHIFT 172 | control->no_banks << FMC_SDCR_NB_SHIFT 173 | control->memory_width << FMC_SDCR_MWID_SHIFT 174 | control->no_rows << FMC_SDCR_NR_SHIFT 175 | control->no_columns << FMC_SDCR_NC_SHIFT, 176 ®s->sdcr2); 177 178 writel(timing->trcd << FMC_SDTR_TRCD_SHIFT 179 | timing->trp << FMC_SDTR_TRP_SHIFT 180 | timing->twr << FMC_SDTR_TWR_SHIFT 181 | timing->trc << FMC_SDTR_TRC_SHIFT 182 | timing->tras << FMC_SDTR_TRAS_SHIFT 183 | timing->txsr << FMC_SDTR_TXSR_SHIFT 184 | timing->tmrd << FMC_SDTR_TMRD_SHIFT, 185 ®s->sdtr1); 186 187 if (target_bank == SDRAM_BANK2) 188 writel(timing->trcd << FMC_SDTR_TRCD_SHIFT 189 | timing->trp << FMC_SDTR_TRP_SHIFT 190 | timing->twr << FMC_SDTR_TWR_SHIFT 191 | timing->trc << FMC_SDTR_TRC_SHIFT 192 | timing->tras << FMC_SDTR_TRAS_SHIFT 193 | timing->txsr << FMC_SDTR_TXSR_SHIFT 194 | timing->tmrd << FMC_SDTR_TMRD_SHIFT, 195 ®s->sdtr2); 196 if (target_bank == SDRAM_BANK1) 197 ctb = FMC_SDCMR_BANK_1; 198 else 199 ctb = FMC_SDCMR_BANK_2; 200 201 writel(ctb | FMC_SDCMR_MODE_START_CLOCK, ®s->sdcmr); 202 udelay(200); /* 200 us delay, page 10, "Power-Up" */ 203 FMC_BUSY_WAIT(regs); 204 205 writel(ctb | FMC_SDCMR_MODE_PRECHARGE, ®s->sdcmr); 206 udelay(100); 207 FMC_BUSY_WAIT(regs); 208 209 writel((ctb | FMC_SDCMR_MODE_AUTOREFRESH | 7 << FMC_SDCMR_NRFS_SHIFT), 210 ®s->sdcmr); 211 udelay(100); 212 FMC_BUSY_WAIT(regs); 213 214 writel(ctb | (SDRAM_MODE_BL << SDRAM_MODE_BL_SHIFT 215 | control->cas_latency << SDRAM_MODE_CAS_SHIFT) 216 << FMC_SDCMR_MODE_REGISTER_SHIFT | FMC_SDCMR_MODE_WRITE_MODE, 217 ®s->sdcmr); 218 udelay(100); 219 FMC_BUSY_WAIT(regs); 220 221 writel(ctb | FMC_SDCMR_MODE_NORMAL, ®s->sdcmr); 222 FMC_BUSY_WAIT(regs); 223 224 /* Refresh timer */ 225 writel(ref_count << 1, ®s->sdrtr); 226 } 227 228 return 0; 229 } 230 231 static int stm32_fmc_ofdata_to_platdata(struct udevice *dev) 232 { 233 struct stm32_sdram_params *params = dev_get_platdata(dev); 234 struct bank_params *bank_params; 235 ofnode bank_node; 236 char *bank_name; 237 u8 bank = 0; 238 239 dev_for_each_subnode(bank_node, dev) { 240 /* extract the bank index from DT */ 241 bank_name = (char *)ofnode_get_name(bank_node); 242 strsep(&bank_name, "@"); 243 if (!bank_name) { 244 error("missing sdram bank index"); 245 return -EINVAL; 246 } 247 248 bank_params = ¶ms->bank_params[bank]; 249 strict_strtoul(bank_name, 10, 250 (long unsigned int *)&bank_params->target_bank); 251 252 if (bank_params->target_bank >= MAX_SDRAM_BANK) { 253 error("Found bank %d , but only bank 0 and 1 are supported", 254 bank_params->target_bank); 255 return -EINVAL; 256 } 257 258 debug("Find bank %s %u\n", bank_name, bank_params->target_bank); 259 260 params->bank_params[bank].sdram_control = 261 (struct stm32_sdram_control *) 262 ofnode_read_u8_array_ptr(bank_node, 263 "st,sdram-control", 264 sizeof(struct stm32_sdram_control)); 265 266 if (!params->bank_params[bank].sdram_control) { 267 error("st,sdram-control not found for %s", 268 ofnode_get_name(bank_node)); 269 return -EINVAL; 270 } 271 272 273 params->bank_params[bank].sdram_timing = 274 (struct stm32_sdram_timing *) 275 ofnode_read_u8_array_ptr(bank_node, 276 "st,sdram-timing", 277 sizeof(struct stm32_sdram_timing)); 278 279 if (!params->bank_params[bank].sdram_timing) { 280 error("st,sdram-timing not found for %s", 281 ofnode_get_name(bank_node)); 282 return -EINVAL; 283 } 284 285 286 bank_params->sdram_ref_count = ofnode_read_u32_default(bank_node, 287 "st,sdram-refcount", 8196); 288 bank++; 289 } 290 291 params->no_sdram_banks = bank; 292 debug("%s, no of banks = %d\n", __func__, params->no_sdram_banks); 293 294 return 0; 295 } 296 297 static int stm32_fmc_probe(struct udevice *dev) 298 { 299 struct stm32_sdram_params *params = dev_get_platdata(dev); 300 int ret; 301 fdt_addr_t addr; 302 303 addr = dev_read_addr(dev); 304 if (addr == FDT_ADDR_T_NONE) 305 return -EINVAL; 306 307 params->base = (struct stm32_fmc_regs *)addr; 308 309 #ifdef CONFIG_CLK 310 struct clk clk; 311 312 ret = clk_get_by_index(dev, 0, &clk); 313 if (ret < 0) 314 return ret; 315 316 ret = clk_enable(&clk); 317 318 if (ret) { 319 dev_err(dev, "failed to enable clock\n"); 320 return ret; 321 } 322 #endif 323 ret = stm32_sdram_init(dev); 324 if (ret) 325 return ret; 326 327 return 0; 328 } 329 330 static int stm32_fmc_get_info(struct udevice *dev, struct ram_info *info) 331 { 332 return 0; 333 } 334 335 static struct ram_ops stm32_fmc_ops = { 336 .get_info = stm32_fmc_get_info, 337 }; 338 339 static const struct udevice_id stm32_fmc_ids[] = { 340 { .compatible = "st,stm32-fmc" }, 341 { } 342 }; 343 344 U_BOOT_DRIVER(stm32_fmc) = { 345 .name = "stm32_fmc", 346 .id = UCLASS_RAM, 347 .of_match = stm32_fmc_ids, 348 .ops = &stm32_fmc_ops, 349 .ofdata_to_platdata = stm32_fmc_ofdata_to_platdata, 350 .probe = stm32_fmc_probe, 351 .platdata_auto_alloc_size = sizeof(struct stm32_sdram_params), 352 }; 353