| d054c2f8 | 28-Oct-2015 |
Dirk Eibach <dirk.eibach@gdsys.cc> |
board: gdsys: Consider DP501 limits on link training
DP501 only supports DP 1.1a.
Limit settings for link bandwidth and lane count to
values allowed by DP 1.1a.
Signed-off-by: Dirk Eibach <dirk.eib
board: gdsys: Consider DP501 limits on link training
DP501 only supports DP 1.1a.
Limit settings for link bandwidth and lane count to
values allowed by DP 1.1a.
Signed-off-by: Dirk Eibach <dirk.eibach@gdsys.cc>
show more ...
|
| 2302fd32 | 28-Oct-2015 |
Dirk Eibach <dirk.eibach@gdsys.cc> |
board: gdsys: Increase DP501 I2C retry interval
With Club 3D dual link adapter there are AUX-channel timeouts
when EDID is read. Increasing retry interval time to max (400us)
fixes this.
Signed-off
board: gdsys: Increase DP501 I2C retry interval
With Club 3D dual link adapter there are AUX-channel timeouts
when EDID is read. Increasing retry interval time to max (400us)
fixes this.
Signed-off-by: Dirk Eibach <dirk.eibach@gdsys.cc>
Reviewed-by: Heiko Schocher <hs@denx.de>
show more ...
|
| b415fec6 | 03-Jul-2014 |
Dirk Eibach <dirk.eibach@gdsys.cc> |
board: gdsys: Enable scrambling on DP501
For proper displayport performance, scrambling has to be enabled, but
is turned off on DP501 by default.
Signed-off-by: Dirk Eibach <dirk.eibach@gdsys.cc> |
| 0f0c1021 | 26-Jun-2013 |
Dirk Eibach <eibach@gdsys.de> |
powerpc/ppc4xx: Consider gdsys FPGA OSD size
OSD size was constant 32x16 characters.
Now the size is set as announced by the FPGA.
Signed-off-by: Dirk Eibach <dirk.eibach@gdsys.cc>
Signed-off-by: S
powerpc/ppc4xx: Consider gdsys FPGA OSD size
OSD size was constant 32x16 characters.
Now the size is set as announced by the FPGA.
Signed-off-by: Dirk Eibach <dirk.eibach@gdsys.cc>
Signed-off-by: Stefan Roese <sr@denx.de>
show more ...
|