1 /* 2 * (C) Copyright 2014 3 * Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8 #include <common.h> 9 #include <hwconfig.h> 10 #include <i2c.h> 11 #include <spi.h> 12 #include <libfdt.h> 13 #include <fdt_support.h> 14 #include <pci.h> 15 #include <mpc83xx.h> 16 #include <fsl_esdhc.h> 17 #include <asm/io.h> 18 #include <asm/fsl_serdes.h> 19 #include <asm/fsl_mpc83xx_serdes.h> 20 21 #include "mpc8308.h" 22 23 #include <gdsys_fpga.h> 24 25 #include "../common/adv7611.h" 26 #include "../common/ch7301.h" 27 #include "../common/ioep-fpga.h" 28 #include "../common/mclink.h" 29 #include "../common/osd.h" 30 #include "../common/phy.h" 31 32 #include <pca953x.h> 33 #include <pca9698.h> 34 35 #include <miiphy.h> 36 37 DECLARE_GLOBAL_DATA_PTR; 38 39 #define MAX_MUX_CHANNELS 2 40 41 enum { 42 MCFPGA_DONE = 1 << 0, 43 MCFPGA_INIT_N = 1 << 1, 44 MCFPGA_PROGRAM_N = 1 << 2, 45 MCFPGA_UPDATE_ENABLE_N = 1 << 3, 46 MCFPGA_RESET_N = 1 << 4, 47 }; 48 49 enum { 50 GPIO_MDC = 1 << 14, 51 GPIO_MDIO = 1 << 15, 52 }; 53 54 enum { 55 FAN_CONFIG = 0x03, 56 FAN_TACHLIM_LSB = 0x48, 57 FAN_TACHLIM_MSB = 0x49, 58 FAN_PWM_FREQ = 0x4D, 59 }; 60 61 unsigned int mclink_fpgacount; 62 struct ihs_fpga *fpga_ptr[] = CONFIG_SYS_FPGA_PTR; 63 64 struct { 65 u8 bus; 66 u8 addr; 67 } strider_fans[] = CONFIG_STRIDER_FANS; 68 69 int fpga_set_reg(u32 fpga, u16 *reg, off_t regoff, u16 data) 70 { 71 int res; 72 73 switch (fpga) { 74 case 0: 75 out_le16(reg, data); 76 break; 77 default: 78 res = mclink_send(fpga - 1, regoff, data); 79 if (res < 0) { 80 printf("mclink_send reg %02lx data %04x returned %d\n", 81 regoff, data, res); 82 return res; 83 } 84 break; 85 } 86 87 return 0; 88 } 89 90 int fpga_get_reg(u32 fpga, u16 *reg, off_t regoff, u16 *data) 91 { 92 int res; 93 94 switch (fpga) { 95 case 0: 96 *data = in_le16(reg); 97 break; 98 default: 99 if (fpga > mclink_fpgacount) 100 return -EINVAL; 101 res = mclink_receive(fpga - 1, regoff, data); 102 if (res < 0) { 103 printf("mclink_receive reg %02lx returned %d\n", 104 regoff, res); 105 return res; 106 } 107 } 108 109 return 0; 110 } 111 112 int checkboard(void) 113 { 114 char *s = getenv("serial#"); 115 bool hw_type_cat = pca9698_get_value(0x20, 18); 116 117 puts("Board: "); 118 119 printf("Strider %s", hw_type_cat ? "CAT" : "Fiber"); 120 121 if (s != NULL) { 122 puts(", serial# "); 123 puts(s); 124 } 125 126 puts("\n"); 127 128 return 0; 129 } 130 131 static void init_fan_controller(u8 addr) 132 { 133 int val; 134 135 /* set PWM Frequency to 2.5% resolution */ 136 i2c_reg_write(addr, FAN_PWM_FREQ, 20); 137 138 /* set Tachometer Limit */ 139 i2c_reg_write(addr, FAN_TACHLIM_LSB, 0x10); 140 i2c_reg_write(addr, FAN_TACHLIM_MSB, 0x0a); 141 142 /* enable Tach input */ 143 val = i2c_reg_read(addr, FAN_CONFIG) | 0x04; 144 i2c_reg_write(addr, FAN_CONFIG, val); 145 } 146 147 int last_stage_init(void) 148 { 149 int slaves; 150 unsigned int k; 151 unsigned int mux_ch; 152 unsigned char mclink_controllers[] = { 0x3c, 0x3d, 0x3e }; 153 bool hw_type_cat = pca9698_get_value(0x20, 18); 154 bool ch0_sgmii2_present = false; 155 156 /* Turn on Analog Devices ADV7611 */ 157 pca9698_direction_output(0x20, 8, 0); 158 159 /* Turn on Parade DP501 */ 160 pca9698_direction_output(0x20, 9, 1); 161 162 ch0_sgmii2_present = !pca9698_get_value(0x20, 37); 163 164 /* wait for FPGA done, then reset FPGA */ 165 for (k = 0; k < ARRAY_SIZE(mclink_controllers); ++k) { 166 unsigned int ctr = 0; 167 168 if (i2c_probe(mclink_controllers[k])) 169 continue; 170 171 while (!(pca953x_get_val(mclink_controllers[k]) 172 & MCFPGA_DONE)) { 173 udelay(100000); 174 if (ctr++ > 5) { 175 printf("no done for mclink_controller %d\n", k); 176 break; 177 } 178 } 179 180 pca953x_set_dir(mclink_controllers[k], MCFPGA_RESET_N, 0); 181 pca953x_set_val(mclink_controllers[k], MCFPGA_RESET_N, 0); 182 udelay(10); 183 pca953x_set_val(mclink_controllers[k], MCFPGA_RESET_N, 184 MCFPGA_RESET_N); 185 } 186 187 if (hw_type_cat) { 188 miiphy_register(bb_miiphy_buses[0].name, bb_miiphy_read, 189 bb_miiphy_write); 190 for (mux_ch = 0; mux_ch < MAX_MUX_CHANNELS; ++mux_ch) { 191 if ((mux_ch == 1) && !ch0_sgmii2_present) 192 continue; 193 194 setup_88e1514(bb_miiphy_buses[0].name, mux_ch); 195 } 196 } 197 198 /* give slave-PLLs and Parade DP501 some time to be up and running */ 199 udelay(500000); 200 201 mclink_fpgacount = CONFIG_SYS_MCLINK_MAX; 202 slaves = mclink_probe(); 203 mclink_fpgacount = 0; 204 205 ioep_fpga_print_info(0); 206 207 if (!adv7611_probe(0)) 208 printf(" Advantiv ADV7611 HDMI Receiver\n"); 209 210 #ifdef CONFIG_STRIDER_CON 211 if (ioep_fpga_has_osd(0)) 212 osd_probe(0); 213 #endif 214 215 #ifdef CONFIG_STRIDER_CPU 216 ch7301_probe(0, false); 217 #endif 218 219 if (slaves <= 0) 220 return 0; 221 222 mclink_fpgacount = slaves; 223 224 for (k = 1; k <= slaves; ++k) { 225 ioep_fpga_print_info(k); 226 #ifdef CONFIG_STRIDER_CON 227 if (ioep_fpga_has_osd(k)) 228 osd_probe(k); 229 #endif 230 #ifdef CONFIG_STRIDER_CPU 231 FPGA_SET_REG(k, extended_control, 0); /* enable video in*/ 232 if (!adv7611_probe(k)) 233 printf(" Advantiv ADV7611 HDMI Receiver\n"); 234 ch7301_probe(k, false); 235 #endif 236 if (hw_type_cat) { 237 miiphy_register(bb_miiphy_buses[k].name, 238 bb_miiphy_read, bb_miiphy_write); 239 setup_88e1514(bb_miiphy_buses[k].name, 0); 240 } 241 } 242 243 for (k = 0; k < ARRAY_SIZE(strider_fans); ++k) { 244 i2c_set_bus_num(strider_fans[k].bus); 245 init_fan_controller(strider_fans[k].addr); 246 } 247 248 return 0; 249 } 250 251 /* 252 * provide access to fpga gpios (for I2C bitbang) 253 * (these may look all too simple but make iocon.h much more readable) 254 */ 255 void fpga_gpio_set(unsigned int bus, int pin) 256 { 257 FPGA_SET_REG(bus, gpio.set, pin); 258 } 259 260 void fpga_gpio_clear(unsigned int bus, int pin) 261 { 262 FPGA_SET_REG(bus, gpio.clear, pin); 263 } 264 265 int fpga_gpio_get(unsigned int bus, int pin) 266 { 267 u16 val; 268 269 FPGA_GET_REG(bus, gpio.read, &val); 270 271 return val & pin; 272 } 273 274 void mpc8308_init(void) 275 { 276 pca9698_direction_output(0x20, 26, 1); 277 } 278 279 void mpc8308_set_fpga_reset(unsigned state) 280 { 281 pca9698_set_value(0x20, 26, state ? 0 : 1); 282 } 283 284 void mpc8308_setup_hw(void) 285 { 286 immap_t *immr = (immap_t *)CONFIG_SYS_IMMR; 287 288 /* 289 * set "startup-finished"-gpios 290 */ 291 setbits_be32(&immr->gpio[0].dir, (1 << (31-11)) | (1 << (31-12))); 292 setbits_be32(&immr->gpio[0].dat, 1 << (31-12)); 293 } 294 295 int mpc8308_get_fpga_done(unsigned fpga) 296 { 297 return pca9698_get_value(0x20, 20); 298 } 299 300 #ifdef CONFIG_FSL_ESDHC 301 int board_mmc_init(bd_t *bd) 302 { 303 immap_t *immr = (immap_t *)CONFIG_SYS_IMMR; 304 sysconf83xx_t *sysconf = &immr->sysconf; 305 306 /* Enable cache snooping in eSDHC system configuration register */ 307 out_be32(&sysconf->sdhccr, 0x02000000); 308 309 return fsl_esdhc_mmc_init(bd); 310 } 311 #endif 312 313 static struct pci_region pcie_regions_0[] = { 314 { 315 .bus_start = CONFIG_SYS_PCIE1_MEM_BASE, 316 .phys_start = CONFIG_SYS_PCIE1_MEM_PHYS, 317 .size = CONFIG_SYS_PCIE1_MEM_SIZE, 318 .flags = PCI_REGION_MEM, 319 }, 320 { 321 .bus_start = CONFIG_SYS_PCIE1_IO_BASE, 322 .phys_start = CONFIG_SYS_PCIE1_IO_PHYS, 323 .size = CONFIG_SYS_PCIE1_IO_SIZE, 324 .flags = PCI_REGION_IO, 325 }, 326 }; 327 328 void pci_init_board(void) 329 { 330 immap_t *immr = (immap_t *)CONFIG_SYS_IMMR; 331 sysconf83xx_t *sysconf = &immr->sysconf; 332 law83xx_t *pcie_law = sysconf->pcielaw; 333 struct pci_region *pcie_reg[] = { pcie_regions_0 }; 334 335 fsl_setup_serdes(CONFIG_FSL_SERDES1, FSL_SERDES_PROTO_PEX, 336 FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V); 337 338 /* Deassert the resets in the control register */ 339 out_be32(&sysconf->pecr1, 0xE0008000); 340 udelay(2000); 341 342 /* Configure PCI Express Local Access Windows */ 343 out_be32(&pcie_law[0].bar, CONFIG_SYS_PCIE1_BASE & LAWBAR_BAR); 344 out_be32(&pcie_law[0].ar, LBLAWAR_EN | LBLAWAR_512MB); 345 346 mpc83xx_pcie_init(1, pcie_reg); 347 } 348 349 ulong board_flash_get_legacy(ulong base, int banknum, flash_info_t *info) 350 { 351 info->portwidth = FLASH_CFI_16BIT; 352 info->chipwidth = FLASH_CFI_BY16; 353 info->interface = FLASH_CFI_X16; 354 return 1; 355 } 356 357 #if defined(CONFIG_OF_BOARD_SETUP) 358 int ft_board_setup(void *blob, bd_t *bd) 359 { 360 ft_cpu_setup(blob, bd); 361 fdt_fixup_dr_usb(blob, bd); 362 fdt_fixup_esdhc(blob, bd); 363 364 return 0; 365 } 366 #endif 367 368 /* 369 * FPGA MII bitbang implementation 370 */ 371 372 struct fpga_mii { 373 unsigned fpga; 374 int mdio; 375 } fpga_mii[] = { 376 { 0, 1}, 377 { 1, 1}, 378 { 2, 1}, 379 { 3, 1}, 380 }; 381 382 static int mii_dummy_init(struct bb_miiphy_bus *bus) 383 { 384 return 0; 385 } 386 387 static int mii_mdio_active(struct bb_miiphy_bus *bus) 388 { 389 struct fpga_mii *fpga_mii = bus->priv; 390 391 if (fpga_mii->mdio) 392 FPGA_SET_REG(fpga_mii->fpga, gpio.set, GPIO_MDIO); 393 else 394 FPGA_SET_REG(fpga_mii->fpga, gpio.clear, GPIO_MDIO); 395 396 return 0; 397 } 398 399 static int mii_mdio_tristate(struct bb_miiphy_bus *bus) 400 { 401 struct fpga_mii *fpga_mii = bus->priv; 402 403 FPGA_SET_REG(fpga_mii->fpga, gpio.set, GPIO_MDIO); 404 405 return 0; 406 } 407 408 static int mii_set_mdio(struct bb_miiphy_bus *bus, int v) 409 { 410 struct fpga_mii *fpga_mii = bus->priv; 411 412 if (v) 413 FPGA_SET_REG(fpga_mii->fpga, gpio.set, GPIO_MDIO); 414 else 415 FPGA_SET_REG(fpga_mii->fpga, gpio.clear, GPIO_MDIO); 416 417 fpga_mii->mdio = v; 418 419 return 0; 420 } 421 422 static int mii_get_mdio(struct bb_miiphy_bus *bus, int *v) 423 { 424 u16 gpio; 425 struct fpga_mii *fpga_mii = bus->priv; 426 427 FPGA_GET_REG(fpga_mii->fpga, gpio.read, &gpio); 428 429 *v = ((gpio & GPIO_MDIO) != 0); 430 431 return 0; 432 } 433 434 static int mii_set_mdc(struct bb_miiphy_bus *bus, int v) 435 { 436 struct fpga_mii *fpga_mii = bus->priv; 437 438 if (v) 439 FPGA_SET_REG(fpga_mii->fpga, gpio.set, GPIO_MDC); 440 else 441 FPGA_SET_REG(fpga_mii->fpga, gpio.clear, GPIO_MDC); 442 443 return 0; 444 } 445 446 static int mii_delay(struct bb_miiphy_bus *bus) 447 { 448 udelay(1); 449 450 return 0; 451 } 452 453 struct bb_miiphy_bus bb_miiphy_buses[] = { 454 { 455 .name = "board0", 456 .init = mii_dummy_init, 457 .mdio_active = mii_mdio_active, 458 .mdio_tristate = mii_mdio_tristate, 459 .set_mdio = mii_set_mdio, 460 .get_mdio = mii_get_mdio, 461 .set_mdc = mii_set_mdc, 462 .delay = mii_delay, 463 .priv = &fpga_mii[0], 464 }, 465 { 466 .name = "board1", 467 .init = mii_dummy_init, 468 .mdio_active = mii_mdio_active, 469 .mdio_tristate = mii_mdio_tristate, 470 .set_mdio = mii_set_mdio, 471 .get_mdio = mii_get_mdio, 472 .set_mdc = mii_set_mdc, 473 .delay = mii_delay, 474 .priv = &fpga_mii[1], 475 }, 476 { 477 .name = "board2", 478 .init = mii_dummy_init, 479 .mdio_active = mii_mdio_active, 480 .mdio_tristate = mii_mdio_tristate, 481 .set_mdio = mii_set_mdio, 482 .get_mdio = mii_get_mdio, 483 .set_mdc = mii_set_mdc, 484 .delay = mii_delay, 485 .priv = &fpga_mii[2], 486 }, 487 { 488 .name = "board3", 489 .init = mii_dummy_init, 490 .mdio_active = mii_mdio_active, 491 .mdio_tristate = mii_mdio_tristate, 492 .set_mdio = mii_set_mdio, 493 .get_mdio = mii_get_mdio, 494 .set_mdc = mii_set_mdc, 495 .delay = mii_delay, 496 .priv = &fpga_mii[3], 497 }, 498 }; 499 500 int bb_miiphy_buses_num = sizeof(bb_miiphy_buses) / 501 sizeof(bb_miiphy_buses[0]); 502