1 /* 2 * (C) Copyright 2010 3 * Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8 #include <common.h> 9 #include <i2c.h> 10 #include <malloc.h> 11 12 #include "ch7301.h" 13 #include "dp501.h" 14 #include <gdsys_fpga.h> 15 16 #define ICS8N3QV01_I2C_ADDR 0x6E 17 #define ICS8N3QV01_FREF 114285000 18 #define ICS8N3QV01_FREF_LL 114285000LL 19 #define ICS8N3QV01_F_DEFAULT_0 156250000LL 20 #define ICS8N3QV01_F_DEFAULT_1 125000000LL 21 #define ICS8N3QV01_F_DEFAULT_2 100000000LL 22 #define ICS8N3QV01_F_DEFAULT_3 25175000LL 23 24 #define SIL1178_MASTER_I2C_ADDRESS 0x38 25 #define SIL1178_SLAVE_I2C_ADDRESS 0x39 26 27 #define DP501_I2C_ADDR 0x08 28 29 #define PIXCLK_640_480_60 25180000 30 31 #ifdef CONFIG_SYS_OSD_DH 32 #define MAX_OSD_SCREEN 8 33 #define OSD_DH_BASE 4 34 #else 35 #define MAX_OSD_SCREEN 4 36 #endif 37 38 #ifdef CONFIG_SYS_OSD_DH 39 #define OSD_SET_REG(screen, fld, val) \ 40 do { \ 41 if (screen >= OSD_DH_BASE) \ 42 FPGA_SET_REG(screen - OSD_DH_BASE, osd1.fld, val); \ 43 else \ 44 FPGA_SET_REG(screen, osd0.fld, val); \ 45 } while (0) 46 #else 47 #define OSD_SET_REG(screen, fld, val) \ 48 FPGA_SET_REG(screen, osd0.fld, val) 49 #endif 50 51 #ifdef CONFIG_SYS_OSD_DH 52 #define OSD_GET_REG(screen, fld, val) \ 53 do { \ 54 if (screen >= OSD_DH_BASE) \ 55 FPGA_GET_REG(screen - OSD_DH_BASE, osd1.fld, val); \ 56 else \ 57 FPGA_GET_REG(screen, osd0.fld, val); \ 58 } while (0) 59 #else 60 #define OSD_GET_REG(screen, fld, val) \ 61 FPGA_GET_REG(screen, osd0.fld, val) 62 #endif 63 64 unsigned int base_width; 65 unsigned int base_height; 66 size_t bufsize; 67 u16 *buf; 68 69 unsigned int osd_screen_mask = 0; 70 71 #ifdef CONFIG_SYS_ICS8N3QV01_I2C 72 int ics8n3qv01_i2c[] = CONFIG_SYS_ICS8N3QV01_I2C; 73 #endif 74 75 #ifdef CONFIG_SYS_SIL1178_I2C 76 int sil1178_i2c[] = CONFIG_SYS_SIL1178_I2C; 77 #endif 78 79 #ifdef CONFIG_SYS_DP501_I2C 80 int dp501_i2c[] = CONFIG_SYS_DP501_I2C; 81 #endif 82 83 #ifdef CONFIG_SYS_DP501_BASE 84 int dp501_base[] = CONFIG_SYS_DP501_BASE; 85 #endif 86 87 #ifdef CONFIG_SYS_MPC92469AC 88 static void mpc92469ac_calc_parameters(unsigned int fout, 89 unsigned int *post_div, unsigned int *feedback_div) 90 { 91 unsigned int n = *post_div; 92 unsigned int m = *feedback_div; 93 unsigned int a; 94 unsigned int b = 14745600 / 16; 95 96 if (fout < 50169600) 97 n = 8; 98 else if (fout < 100339199) 99 n = 4; 100 else if (fout < 200678399) 101 n = 2; 102 else 103 n = 1; 104 105 a = fout * n + (b / 2); /* add b/2 for proper rounding */ 106 107 m = a / b; 108 109 *post_div = n; 110 *feedback_div = m; 111 } 112 113 static void mpc92469ac_set(unsigned screen, unsigned int fout) 114 { 115 unsigned int n; 116 unsigned int m; 117 unsigned int bitval = 0; 118 mpc92469ac_calc_parameters(fout, &n, &m); 119 120 switch (n) { 121 case 1: 122 bitval = 0x00; 123 break; 124 case 2: 125 bitval = 0x01; 126 break; 127 case 4: 128 bitval = 0x02; 129 break; 130 case 8: 131 bitval = 0x03; 132 break; 133 } 134 135 FPGA_SET_REG(screen, mpc3w_control, (bitval << 9) | m); 136 } 137 #endif 138 139 #ifdef CONFIG_SYS_ICS8N3QV01_I2C 140 141 static unsigned int ics8n3qv01_get_fout_calc(unsigned index) 142 { 143 unsigned long long n; 144 unsigned long long mint; 145 unsigned long long mfrac; 146 u8 reg_a, reg_b, reg_c, reg_d, reg_f; 147 unsigned long long fout_calc; 148 149 if (index > 3) 150 return 0; 151 152 reg_a = i2c_reg_read(ICS8N3QV01_I2C_ADDR, 0 + index); 153 reg_b = i2c_reg_read(ICS8N3QV01_I2C_ADDR, 4 + index); 154 reg_c = i2c_reg_read(ICS8N3QV01_I2C_ADDR, 8 + index); 155 reg_d = i2c_reg_read(ICS8N3QV01_I2C_ADDR, 12 + index); 156 reg_f = i2c_reg_read(ICS8N3QV01_I2C_ADDR, 20 + index); 157 158 mint = ((reg_a >> 1) & 0x1f) | (reg_f & 0x20); 159 mfrac = ((reg_a & 0x01) << 17) | (reg_b << 9) | (reg_c << 1) 160 | (reg_d >> 7); 161 n = reg_d & 0x7f; 162 163 fout_calc = (mint * ICS8N3QV01_FREF_LL 164 + mfrac * ICS8N3QV01_FREF_LL / 262144LL 165 + ICS8N3QV01_FREF_LL / 524288LL 166 + n / 2) 167 / n 168 * 1000000 169 / (1000000 - 100); 170 171 return fout_calc; 172 } 173 174 175 static void ics8n3qv01_calc_parameters(unsigned int fout, 176 unsigned int *_mint, unsigned int *_mfrac, 177 unsigned int *_n) 178 { 179 unsigned int n; 180 unsigned int foutiic; 181 unsigned int fvcoiic; 182 unsigned int mint; 183 unsigned long long mfrac; 184 185 n = (2215000000U + fout / 2) / fout; 186 if ((n & 1) && (n > 5)) 187 n -= 1; 188 189 foutiic = fout - (fout / 10000); 190 fvcoiic = foutiic * n; 191 192 mint = fvcoiic / 114285000; 193 if ((mint < 17) || (mint > 63)) 194 printf("ics8n3qv01_calc_parameters: cannot determine mint\n"); 195 196 mfrac = ((unsigned long long)fvcoiic % 114285000LL) * 262144LL 197 / 114285000LL; 198 199 *_mint = mint; 200 *_mfrac = mfrac; 201 *_n = n; 202 } 203 204 static void ics8n3qv01_set(unsigned int fout) 205 { 206 unsigned int n; 207 unsigned int mint; 208 unsigned int mfrac; 209 unsigned int fout_calc; 210 unsigned long long fout_prog; 211 long long off_ppm; 212 u8 reg0, reg4, reg8, reg12, reg18, reg20; 213 214 fout_calc = ics8n3qv01_get_fout_calc(1); 215 off_ppm = (fout_calc - ICS8N3QV01_F_DEFAULT_1) * 1000000 216 / ICS8N3QV01_F_DEFAULT_1; 217 printf(" PLL is off by %lld ppm\n", off_ppm); 218 fout_prog = (unsigned long long)fout * (unsigned long long)fout_calc 219 / ICS8N3QV01_F_DEFAULT_1; 220 ics8n3qv01_calc_parameters(fout_prog, &mint, &mfrac, &n); 221 222 reg0 = i2c_reg_read(ICS8N3QV01_I2C_ADDR, 0) & 0xc0; 223 reg0 |= (mint & 0x1f) << 1; 224 reg0 |= (mfrac >> 17) & 0x01; 225 i2c_reg_write(ICS8N3QV01_I2C_ADDR, 0, reg0); 226 227 reg4 = mfrac >> 9; 228 i2c_reg_write(ICS8N3QV01_I2C_ADDR, 4, reg4); 229 230 reg8 = mfrac >> 1; 231 i2c_reg_write(ICS8N3QV01_I2C_ADDR, 8, reg8); 232 233 reg12 = mfrac << 7; 234 reg12 |= n & 0x7f; 235 i2c_reg_write(ICS8N3QV01_I2C_ADDR, 12, reg12); 236 237 reg18 = i2c_reg_read(ICS8N3QV01_I2C_ADDR, 18) & 0x03; 238 reg18 |= 0x20; 239 i2c_reg_write(ICS8N3QV01_I2C_ADDR, 18, reg18); 240 241 reg20 = i2c_reg_read(ICS8N3QV01_I2C_ADDR, 20) & 0x1f; 242 reg20 |= mint & (1 << 5); 243 i2c_reg_write(ICS8N3QV01_I2C_ADDR, 20, reg20); 244 } 245 #endif 246 247 static int osd_write_videomem(unsigned screen, unsigned offset, 248 u16 *data, size_t charcount) 249 { 250 unsigned int k; 251 252 for (k = 0; k < charcount; ++k) { 253 if (offset + k >= bufsize) 254 return -1; 255 #ifdef CONFIG_SYS_OSD_DH 256 if (screen >= OSD_DH_BASE) 257 FPGA_SET_REG(screen - OSD_DH_BASE, 258 videomem1[offset + k], data[k]); 259 else 260 FPGA_SET_REG(screen, videomem0[offset + k], data[k]); 261 #else 262 FPGA_SET_REG(screen, videomem0[offset + k], data[k]); 263 #endif 264 } 265 266 return charcount; 267 } 268 269 static int osd_print(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) 270 { 271 unsigned screen; 272 273 if (argc < 5) { 274 cmd_usage(cmdtp); 275 return 1; 276 } 277 278 for (screen = 0; screen < MAX_OSD_SCREEN; ++screen) { 279 unsigned x; 280 unsigned y; 281 unsigned charcount; 282 unsigned len; 283 u8 color; 284 unsigned int k; 285 char *text; 286 int res; 287 288 if (!(osd_screen_mask & (1 << screen))) 289 continue; 290 291 x = simple_strtoul(argv[1], NULL, 16); 292 y = simple_strtoul(argv[2], NULL, 16); 293 color = simple_strtoul(argv[3], NULL, 16); 294 text = argv[4]; 295 charcount = strlen(text); 296 len = (charcount > bufsize) ? bufsize : charcount; 297 298 for (k = 0; k < len; ++k) 299 buf[k] = (text[k] << 8) | color; 300 301 res = osd_write_videomem(screen, y * base_width + x, buf, len); 302 if (res < 0) 303 return res; 304 } 305 306 return 0; 307 } 308 309 int osd_probe(unsigned screen) 310 { 311 u16 version; 312 u16 features; 313 int old_bus = i2c_get_bus_num(); 314 bool pixclock_present = false; 315 bool output_driver_present = false; 316 #ifdef CONFIG_SYS_DP501_I2C 317 #ifdef CONFIG_SYS_DP501_BASE 318 uint8_t dp501_addr = dp501_base[screen]; 319 #else 320 uint8_t dp501_addr = DP501_I2C_ADDR; 321 #endif 322 #endif 323 324 OSD_GET_REG(0, version, &version); 325 OSD_GET_REG(0, features, &features); 326 327 base_width = ((features & 0x3f00) >> 8) + 1; 328 base_height = (features & 0x001f) + 1; 329 bufsize = base_width * base_height; 330 buf = malloc(sizeof(u16) * bufsize); 331 if (!buf) 332 return -1; 333 334 #ifdef CONFIG_SYS_OSD_DH 335 printf("OSD%d-%d: Digital-OSD version %01d.%02d, %d" "x%d characters\n", 336 (screen >= OSD_DH_BASE) ? (screen - OSD_DH_BASE) : screen, 337 (screen > 3) ? 1 : 0, version/100, version%100, base_width, 338 base_height); 339 #else 340 printf("OSD%d: Digital-OSD version %01d.%02d, %d" "x%d characters\n", 341 screen, version/100, version%100, base_width, base_height); 342 #endif 343 /* setup pixclock */ 344 345 #ifdef CONFIG_SYS_MPC92469AC 346 pixclock_present = true; 347 mpc92469ac_set(screen, PIXCLK_640_480_60); 348 #endif 349 350 #ifdef CONFIG_SYS_ICS8N3QV01_I2C 351 i2c_set_bus_num(ics8n3qv01_i2c[screen]); 352 if (!i2c_probe(ICS8N3QV01_I2C_ADDR)) { 353 ics8n3qv01_set(PIXCLK_640_480_60); 354 pixclock_present = true; 355 } 356 #endif 357 358 if (!pixclock_present) 359 printf(" no pixelclock found\n"); 360 361 /* setup output driver */ 362 363 #ifdef CONFIG_SYS_CH7301_I2C 364 if (!ch7301_probe(screen, true)) 365 output_driver_present = true; 366 #endif 367 368 #ifdef CONFIG_SYS_SIL1178_I2C 369 i2c_set_bus_num(sil1178_i2c[screen]); 370 if (!i2c_probe(SIL1178_SLAVE_I2C_ADDRESS)) { 371 if (i2c_reg_read(SIL1178_SLAVE_I2C_ADDRESS, 0x02) == 0x06) { 372 /* 373 * magic initialization sequence, 374 * adapted from datasheet 375 */ 376 i2c_reg_write(SIL1178_SLAVE_I2C_ADDRESS, 0x08, 0x36); 377 i2c_reg_write(SIL1178_MASTER_I2C_ADDRESS, 0x0f, 0x44); 378 i2c_reg_write(SIL1178_MASTER_I2C_ADDRESS, 0x0f, 0x4c); 379 i2c_reg_write(SIL1178_MASTER_I2C_ADDRESS, 0x0e, 0x10); 380 i2c_reg_write(SIL1178_MASTER_I2C_ADDRESS, 0x0a, 0x80); 381 i2c_reg_write(SIL1178_MASTER_I2C_ADDRESS, 0x09, 0x30); 382 i2c_reg_write(SIL1178_MASTER_I2C_ADDRESS, 0x0c, 0x89); 383 i2c_reg_write(SIL1178_MASTER_I2C_ADDRESS, 0x0d, 0x60); 384 i2c_reg_write(SIL1178_MASTER_I2C_ADDRESS, 0x08, 0x36); 385 i2c_reg_write(SIL1178_MASTER_I2C_ADDRESS, 0x08, 0x37); 386 output_driver_present = true; 387 } 388 } 389 #endif 390 391 #ifdef CONFIG_SYS_DP501_I2C 392 i2c_set_bus_num(dp501_i2c[screen]); 393 if (!i2c_probe(dp501_addr)) { 394 dp501_powerup(dp501_addr); 395 output_driver_present = true; 396 } 397 #endif 398 399 if (!output_driver_present) 400 printf(" no output driver found\n"); 401 402 OSD_SET_REG(screen, control, 0x0049); 403 404 OSD_SET_REG(screen, xy_size, ((32 - 1) << 8) | (16 - 1)); 405 OSD_SET_REG(screen, x_pos, 0x007f); 406 OSD_SET_REG(screen, y_pos, 0x005f); 407 408 if (pixclock_present && output_driver_present) 409 osd_screen_mask |= 1 << screen; 410 411 i2c_set_bus_num(old_bus); 412 413 return 0; 414 } 415 416 int osd_write(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) 417 { 418 unsigned screen; 419 420 if ((argc < 4) || (strlen(argv[3]) % 4)) { 421 cmd_usage(cmdtp); 422 return 1; 423 } 424 425 for (screen = 0; screen < MAX_OSD_SCREEN; ++screen) { 426 unsigned x; 427 unsigned y; 428 unsigned k; 429 u16 buffer[base_width]; 430 char *rp; 431 u16 *wp = buffer; 432 unsigned count = (argc > 4) ? 433 simple_strtoul(argv[4], NULL, 16) : 1; 434 435 if (!(osd_screen_mask & (1 << screen))) 436 continue; 437 438 x = simple_strtoul(argv[1], NULL, 16); 439 y = simple_strtoul(argv[2], NULL, 16); 440 rp = argv[3]; 441 442 443 while (*rp) { 444 char substr[5]; 445 446 memcpy(substr, rp, 4); 447 substr[4] = 0; 448 *wp = simple_strtoul(substr, NULL, 16); 449 450 rp += 4; 451 wp++; 452 if (wp - buffer > base_width) 453 break; 454 } 455 456 for (k = 0; k < count; ++k) { 457 unsigned offset = 458 y * base_width + x + k * (wp - buffer); 459 osd_write_videomem(screen, offset, buffer, 460 wp - buffer); 461 } 462 } 463 464 return 0; 465 } 466 467 U_BOOT_CMD( 468 osdw, 5, 0, osd_write, 469 "write 16-bit hex encoded buffer to osd memory", 470 "pos_x pos_y buffer count\n" 471 ); 472 473 U_BOOT_CMD( 474 osdp, 5, 0, osd_print, 475 "write ASCII buffer to osd memory", 476 "pos_x pos_y color text\n" 477 ); 478