| fbb9ecf7 | 05-Aug-2011 |
Timur Tabi <timur@freescale.com> |
powerpc/mp: add support for discontiguous cores
Some SOCs have discontiguously-numbered cores, and so we can't determine the
valid core numbers via the FRR register any more. We define
CPU_TYPE_ENT
powerpc/mp: add support for discontiguous cores
Some SOCs have discontiguously-numbered cores, and so we can't determine the
valid core numbers via the FRR register any more. We define
CPU_TYPE_ENTRY_MASK to specify a discontiguous core mask, and helper functions
to process the mask and enumerate over the set of valid cores.
Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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| f117c0f0 | 01-Aug-2011 |
Kumar Gala <galak@kernel.crashing.org> |
fdt: Rename fdt_create_phandle to fdt_set_phandle
The old fdt_create_phandle didn't actually create a phandle it just
set one. We'll introduce a new helper that actually does creation.
Signed-off-
fdt: Rename fdt_create_phandle to fdt_set_phandle
The old fdt_create_phandle didn't actually create a phandle it just
set one. We'll introduce a new helper that actually does creation.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Acked-by: Gerald Van Baren <vanbaren@cideas.com>
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| e2d0f255 | 31-Jul-2011 |
Kumar Gala <galak@kernel.crashing.org> |
powerpc/85xx: Fix compile warnings/errors if CONFIG_SYS_DPAA_FMAN isn't set
Add ifdef protection around fman specific code related to device tree
clock setup. If we dont have CONFIG_SYS_DPAA_FMAN d
powerpc/85xx: Fix compile warnings/errors if CONFIG_SYS_DPAA_FMAN isn't set
Add ifdef protection around fman specific code related to device tree
clock setup. If we dont have CONFIG_SYS_DPAA_FMAN defined we shouldn't
be executing this code.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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| bc6bbd6b | 07-Jul-2011 |
Poonam Aggrwal <poonam.aggrwal@freescale.com> |
fsl_ifc: Add the workaround for erratum IFC A-003399(enabled on P1010)
Issue: Address masking doesn't work properly.
When sum of the base address, defined by BA, and memory bank size,
defined by AM,
fsl_ifc: Add the workaround for erratum IFC A-003399(enabled on P1010)
Issue: Address masking doesn't work properly.
When sum of the base address, defined by BA, and memory bank size,
defined by AM, exceeds 4GB (0xffff_ffff) then AMASKn[AM] doesn't mask
CSPRn[BA] bits.
Impact:
This will impact booting when we are reprogramming CSPR0(BA) and
AMASK0(AMASK) while executing from NOR Flash.
Workaround:
Re-programming of CSPR(BA) and AMASK is done while not executing from NOR
Flash. The code which programs the BA and AMASK is executed from L2-SRAM.
Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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| fb855f43 | 29-Jun-2011 |
Poonam Aggrwal <poonam.aggrwal@freescale.com> |
powerpc/P1010: Add workaround for erratum P1010-A003549 (related to IFC)
Issue:
Peripheral connected to IFC_CS3 may hamper booting from IFC.
Impact:
Boot from IFC may not be successful if IFC_CS3 i
powerpc/P1010: Add workaround for erratum P1010-A003549 (related to IFC)
Issue:
Peripheral connected to IFC_CS3 may hamper booting from IFC.
Impact:
Boot from IFC may not be successful if IFC_CS3 is used.
Workaround:
If IFC_CS3 is used, gate IFC_CS3 while booting from NAND or NOR.
Also Software should select IFC_CS3 using PMUXCR[26:27] = 0x01.
Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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| 42aee64b | 30-Jun-2011 |
Poonam Aggrwal <poonam.aggrwal@freescale.com> |
fsl_ifc: Add the workaround for erratum IFC-A002769 (enable on P1010)
Issue:
The NOR-FCM does not support access to unaligned addresses for 16 bit port size
Impact:
When 16 bit port size is used, a
fsl_ifc: Add the workaround for erratum IFC-A002769 (enable on P1010)
Issue:
The NOR-FCM does not support access to unaligned addresses for 16 bit port size
Impact:
When 16 bit port size is used, accesses not aligned to 16 bit address boundary
will result in incorrect data
Workaround:
The workaround is to switch to GPCM mode for NOR Flash access.
Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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| e8e6197a | 29-Jun-2011 |
Poonam Aggrwal <poonam.aggrwal@freescale.com> |
powerpc/85xx: Expanding the window of CCSRBAR in AS=1 from 4k to 1M
For an IFC Erratum (A-003399) we will need to access IFC registers in
cpu_init_early_f() so expand the TLB covering CCSR to 1M.
S
powerpc/85xx: Expanding the window of CCSRBAR in AS=1 from 4k to 1M
For an IFC Erratum (A-003399) we will need to access IFC registers in
cpu_init_early_f() so expand the TLB covering CCSR to 1M.
Since we need a TLB to cover 1M we move to using TLB1 array for all the
early mappings so we can cover various sizes beyond 4k.
Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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| 52f90dad | 22-Mar-2011 |
Dipen Dudhat <Dipen.Dudhat@freescale.com> |
nand: Freescale Integrated Flash Controller NAND support
Add NAND support (including spl) on IFC, such as is found on the p1010.
Note that using hardware ECC on IFC with small-page NAND (which is w
nand: Freescale Integrated Flash Controller NAND support
Add NAND support (including spl) on IFC, such as is found on the p1010.
Note that using hardware ECC on IFC with small-page NAND (which is what
comes on the p1010rdb reference board) means there will be insufficient
OOB space for JFFS2, since IFC does not support 1-bit ECC. UBI should
work, as it does not use OOB for anything but ECC.
When hardware ECC is not enabled in CSOR, software ECC is now used.
Signed-off-by: Dipen Dudhat <Dipen.Dudhat@freescale.com>
[scottwood@freescale.com: ECC rework and misc fixes]
Signed-off-by: Scott Wood <scottwood@freescale.com>
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| 6ca88b09 | 03-Aug-2011 |
Timur Tabi <timur@freescale.com> |
powerpc/85xx: relocate CCSR before creating the initial RAM area
Before main memory (DDR) is initialized, the on-chip L1 cache is used as a
memory area for the stack and the global data (gd_t) struc
powerpc/85xx: relocate CCSR before creating the initial RAM area
Before main memory (DDR) is initialized, the on-chip L1 cache is used as a
memory area for the stack and the global data (gd_t) structure. This is
called the initial RAM area, or initram. The L1 cache is locked and the TLBs
point to a non-existent address (so that there's no chance it will overlap
main memory or any device). The L1 cache is also configured not to write
out to memory or the L2 cache, so everything stays in the L1 cache.
One of the things we might do while running out of initram is relocate CCSR.
On reset, CCSR is typically located at some high 32-bit address, like
0xfe000000, and this may not be the best place for CCSR. For example, on
36-bit systems, CCSR is relocated to 0xffe000000, near the top of 36-bit
memory space.
On some future Freescale SOCs, the L1 cache will be forced to write to the
backing store, so we can no longer have the TLBs point to non-existent address.
Instead, we will point the TLBs to an unused area in CCSR. In order for this
technique to work, CCSR needs to be relocated before the initram memory is
enabled.
Unlike the original CCSR relocation code in cpu_init_early_f(), the TLBs
we create now for relocating CCSR are deleted after the relocation is finished.
cpu_init_early_f() will still need to create a TLB for CCSR (at the new
location) for normal U-Boot purposes. This is done to keep the impact to
existing U-Boot code minimal and to better isolate the CCSR relocation code.
Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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| 226502e0 | 16-Sep-2011 |
Stefan Roese <sr@denx.de> |
ppc4xx: Flush dcache after DDR2 autocalibration with caches on
Flush the dcache before removing the TLB with caches enabled.
Otherwise this might lead to problems later on, e.g. while booting
Linux
ppc4xx: Flush dcache after DDR2 autocalibration with caches on
Flush the dcache before removing the TLB with caches enabled.
Otherwise this might lead to problems later on, e.g. while booting
Linux (as seen on ICON-440SPe).
Signed-off-by: Stefan Roese <sr@denx.de>
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| fa82f871 | 04-Aug-2011 |
Albert ARIBAUD <albert.u.boot@aribaud.net> |
Convert ISO-8859 files to UTF-8
There was a mix of UTF-8 and ISO-8859 files in the U-Boot source
tree, which could cause issues with the patchwork review system.
This commit converts all ISO-8859 fi
Convert ISO-8859 files to UTF-8
There was a mix of UTF-8 and ISO-8859 files in the U-Boot source
tree, which could cause issues with the patchwork review system.
This commit converts all ISO-8859 files to UTF-8.
Signed-off-by: Albert ARIBAUD <albert.u.boot@aribaud.net>
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| 3b4a2263 | 26-May-2011 |
Timur Tabi <timur@freescale.com> |
video: Add SHARP LQ084S3LG01 LCD support on P1022DS
The SHARP LQ084S3LG01 is a TFT LCD used on the P1022DS (revision "C") board.
This device only supports 800x600 resolution, so if that resolution i
video: Add SHARP LQ084S3LG01 LCD support on P1022DS
The SHARP LQ084S3LG01 is a TFT LCD used on the P1022DS (revision "C") board.
This device only supports 800x600 resolution, so if that resolution is selected,
assume that this is the device. The device is attached to the LVDS port
on the P1022DS board.
The existing 800x600 entry (for the PDM360NG board) is actually 800x480,
so we fix that. To support two different 800x resolutions, the Y-resolution
is now passed to fsl_diu_init() and both values are used to pick the proper
fb_videomode structure.
The data for the 800x600 video mode is originally from Jiang Yutang.
Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Jiang Yutang <b14898@freescale.com>
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| 57567361 | 29-Jul-2011 |
Kumar Gala <galak@kernel.crashing.org> |
powerpc/8xxx: Remove dependency on <usb.h>
We used <usb.h> for USB_MAX_DEVICE. However this requires we actual
build in support for USB into u-boot (which should not be required for
device tree fix
powerpc/8xxx: Remove dependency on <usb.h>
We used <usb.h> for USB_MAX_DEVICE. However this requires we actual
build in support for USB into u-boot (which should not be required for
device tree fixup).
At this time no FSL SoC that utilizies this code (83xx/85xx) has more
than 2 USB controllers. So we replace USB_MAX_DEVICE with a local
define FSL_MAX_NUM_USB_CTRLS.
If/when a device shows up with more than 2 controllers we can easily
bump this value or refactor into a proper define per SoC.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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| a3a3e7b2 | 28-Jul-2011 |
Shaohui Xie <Shaohui.Xie@freescale.com> |
powerpc/85xx: enable USB2 gadget mode for corenet ds board
to make USB2 worked in gadget mode, we need to set it's 'dr_mode' to
'peripheral' in hwconfig, but driver starts scan from 'usb1', it'll br
powerpc/85xx: enable USB2 gadget mode for corenet ds board
to make USB2 worked in gadget mode, we need to set it's 'dr_mode' to
'peripheral' in hwconfig, but driver starts scan from 'usb1', it'll break
out if it cannot find 'usb1', so drop the 'else' clause to make driver scan
all the 'usbx'.
Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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| 90f89f09 | 03-May-2011 |
Timur Tabi <timur@freescale.com> |
powerpc/85xx: verify the device tree before booting Linux
Introduce ft_verify_fdt(), a function that is called after the device tree
has been fixed up, that displays warning messages if there is a m
powerpc/85xx: verify the device tree before booting Linux
Introduce ft_verify_fdt(), a function that is called after the device tree
has been fixed up, that displays warning messages if there is a mismatch
between the physical addresses of some devices that U-Boot has configured
with what the device tree says the addresses are.
This is a particular problem when booting a 36-bit device tree from a
32-bit U-Boot (or vice versa), because the physical address of CCSR is
wrong in the device tree. When the operating system boots, no messages are
displayed, so the user generally has no idea what's wrong.
Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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| 21cd5815 | 25-Jul-2011 |
Wolfgang Denk <wd@denx.de> |
MPC8xxx: drop redundant boot messages
Current code would print RAM size information like this:
DRAM: DDR: 256 MiB (DDR1, 64-bit, CL=2, ECC off)
Turn a number of printf()s into debug() to get rid
MPC8xxx: drop redundant boot messages
Current code would print RAM size information like this:
DRAM: DDR: 256 MiB (DDR1, 64-bit, CL=2, ECC off)
Turn a number of printf()s into debug() to get rid of the redundant
"DDR: " string like this:
DRAM: 256 MiB (DDR1, 64-bit, CL=2, ECC off)
Signed-off-by: Wolfgang Denk <wd@denx.de>
Acked-by: York Sun <yorksun@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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|
| 8992738d | 25-Jul-2011 |
Kumar Gala <galak@kernel.crashing.org> |
powerpc/85xx: Cleanup handling of PVR detection for e500/e500mc/e5500
At some point we broke the detection of e500v1 class cores. Fix that
and simply the code to just utilize PVR_VER() to have a si
powerpc/85xx: Cleanup handling of PVR detection for e500/e500mc/e5500
At some point we broke the detection of e500v1 class cores. Fix that
and simply the code to just utilize PVR_VER() to have a single case
statement.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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|
| 65bb8b06 | 04-Mar-2011 |
Bhaskar Upadhaya <Bhaskar.Upadhaya@freescale.com> |
powerpc/85xx: Fix up clock_freq property in CAN node of dts
Fix up the device tree property associated with the Flexcan clock
frequency. This property is used to calculate the bit timing parameters
powerpc/85xx: Fix up clock_freq property in CAN node of dts
Fix up the device tree property associated with the Flexcan clock
frequency. This property is used to calculate the bit timing parameters
for Flexcan.
Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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| 0a9fe8ee | 23-May-2011 |
Matthew McClintock <msm@freescale.com> |
powerpc/85xx: provide 85xx flush_icache for cmd_cache
This provides a function that will override the weak function
flush_icache to let 85xx boards to flush the icache
cc: Kumar Gala <kumar.gala@fr
powerpc/85xx: provide 85xx flush_icache for cmd_cache
This provides a function that will override the weak function
flush_icache to let 85xx boards to flush the icache
cc: Kumar Gala <kumar.gala@freescale.com>
Signed-off-by: Matthew McClintock <msm@freescale.com>
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| acf3f8da | 21-Jul-2011 |
Kumar Gala <galak@kernel.crashing.org> |
powerpc/85xx: Handle the lack of L2 cache on P2040/P2040E
The P2040/P2040E have no L2 cache. So we utilize the SVR to determine
if we are one of these devices and skip the L2 init code in cpu_init.
powerpc/85xx: Handle the lack of L2 cache on P2040/P2040E
The P2040/P2040E have no L2 cache. So we utilize the SVR to determine
if we are one of these devices and skip the L2 init code in cpu_init.c
and release. For the device tree we skip the updating of the L2 cache
properties but we still update the chain of caches so the CPC/L3 node
can be properly updated.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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| db564bcc | 21-Jul-2011 |
Kumar Gala <galak@kernel.crashing.org> |
powerpc/85xx: Add support for P2041[e] XAUI in SERDES
We add XAUI_FM1 into the SERDES tables for P2041[e] devices. However
for the P2040[e] devices that dont support XAUI we handle this at
runtime
powerpc/85xx: Add support for P2041[e] XAUI in SERDES
We add XAUI_FM1 into the SERDES tables for P2041[e] devices. However
for the P2040[e] devices that dont support XAUI we handle this at
runtime via SVR checks. If we are on a P2040[e] device the SERDES
functions will behave as follows:
is_serdes_prtcl_valid() will always report invalid if prtcl passed in is
XAUI_FM1.
serdes_get_prtcl() will report NONE if the prtcl in the table is set to
XAUI_FM1.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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| 88b91f2d | 21-Jul-2011 |
Kumar Gala <galak@kernel.crashing.org> |
powerpc/85xx: Rename P2040 id & SERDES to P2041
P2041 is the superset part that covers both P2040 & P2041. The only
difference between the two devices is that P2041 supports 10g/XAUI and
has an L2
powerpc/85xx: Rename P2040 id & SERDES to P2041
P2041 is the superset part that covers both P2040 & P2041. The only
difference between the two devices is that P2041 supports 10g/XAUI and
has an L2 cache.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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| f110fe94 | 20-Jul-2011 |
Stephen George <stephen.george@freescale.com> |
powerpc/85xx: Adding configuration for DCSRCR to enable 32M access
Configuring DCSRCR to define the DCSR space to be 1G instead
of the default 4M. DCSRCR only allows selection of either 4M
or 1G.
Mo
powerpc/85xx: Adding configuration for DCSRCR to enable 32M access
Configuring DCSRCR to define the DCSR space to be 1G instead
of the default 4M. DCSRCR only allows selection of either 4M
or 1G.
Most DCSR registers are within 4M but the Nexus trace buffer
is located at offset 16M within the DCSR.
Configuring the LAW to be 32M to allow access to the Nexus
trace buffer. No TLB modification is required since accessing
the Nexus trace buffer from within u-boot is not required.
Signed-off-by: Stephen George <stephen.george@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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| 09c2e90c | 18-Jul-2011 |
Andreas Bießmann <andreas.devel@googlemail.com> |
unify version_string
This patch removes the architecture specific implementation of
version_string where possible. Some architectures use a special place
and therefore we provide U_BOOT_VERSION_STRI
unify version_string
This patch removes the architecture specific implementation of
version_string where possible. Some architectures use a special place
and therefore we provide U_BOOT_VERSION_STRING definition and a common
weak symbol version_string.
Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
CC: Mike Frysinger <vapier@gentoo.org>
CC: Peter Pan <pppeterpppan@gmail.com>
Acked-by: Mike Frysinger <vapier@gentoo.org>
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| 1c9a5606 | 29-Apr-2011 |
Mike Frysinger <vapier@gentoo.org> |
serial: drop useless ctlr field
The multi serial support has a "ctlr" field which almost no one uses,
but everyone is forced to set to useless strings. So punt it.
Funny enough, the only code that
serial: drop useless ctlr field
The multi serial support has a "ctlr" field which almost no one uses,
but everyone is forced to set to useless strings. So punt it.
Funny enough, the only code that actually reads this field (the mpc8xx
driver) has a typo where it meant to look for the SCC driver. Fix it
while converting the check to use the name field.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
CC: Heiko Schocher <hs@denx.de>
CC: Anatolij Gustschin <agust@denx.de>
CC: Tom Rix <Tom.Rix@windriver.com>
CC: Minkyu Kang <mk7.kang@samsung.com>
CC: Craig Nauman <cnauman@diagraph.com>
CC: Marek Vasut <marek.vasut@gmail.com>
CC: Prafulla Wadaskar <prafulla@marvell.com>
CC: Mahavir Jain <mjain@marvell.com>
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