1 /* 2 * Copyright 2011 Freescale Semiconductor, Inc. 3 * 4 * This program is free software; you can redistribute it and/or 5 * modify it under the terms of the GNU General Public License as 6 * published by the Free Software Foundation; either version 2 of 7 * the License, or (at your option) any later version. 8 * 9 * This program is distributed in the hope that it will be useful, 10 * but WITHOUT ANY WARRANTY; without even the implied warranty of 11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 * GNU General Public License for more details. 13 * 14 * You should have received a copy of the GNU General Public License 15 * along with this program; if not, write to the Free Software 16 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 17 * MA 02111-1307 USA 18 * 19 */ 20 21 #ifndef _ASM_MPC85xx_CONFIG_H_ 22 #define _ASM_MPC85xx_CONFIG_H_ 23 24 /* SoC specific defines for Freescale MPC85xx (PQ3) and QorIQ processors */ 25 26 #ifdef CONFIG_SYS_CCSRBAR_DEFAULT 27 #error "Do not define CONFIG_SYS_CCSRBAR_DEFAULT in the board header file." 28 #endif 29 30 /* Number of TLB CAM entries we have on FSL Book-E chips */ 31 #if defined(CONFIG_E500MC) 32 #define CONFIG_SYS_NUM_TLBCAMS 64 33 #elif defined(CONFIG_E500) 34 #define CONFIG_SYS_NUM_TLBCAMS 16 35 #endif 36 37 #if defined(CONFIG_MPC8536) 38 #define CONFIG_MAX_CPUS 1 39 #define CONFIG_SYS_FSL_NUM_LAWS 12 40 #define CONFIG_SYS_FSL_SEC_COMPAT 2 41 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 42 43 #elif defined(CONFIG_MPC8540) 44 #define CONFIG_MAX_CPUS 1 45 #define CONFIG_SYS_FSL_NUM_LAWS 8 46 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 47 48 #elif defined(CONFIG_MPC8541) 49 #define CONFIG_MAX_CPUS 1 50 #define CONFIG_SYS_FSL_NUM_LAWS 8 51 #define CONFIG_SYS_FSL_SEC_COMPAT 2 52 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 53 54 #elif defined(CONFIG_MPC8544) 55 #define CONFIG_MAX_CPUS 1 56 #define CONFIG_SYS_FSL_NUM_LAWS 10 57 #define CONFIG_SYS_FSL_SEC_COMPAT 2 58 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 59 60 #elif defined(CONFIG_MPC8548) 61 #define CONFIG_MAX_CPUS 1 62 #define CONFIG_SYS_FSL_NUM_LAWS 10 63 #define CONFIG_SYS_FSL_SEC_COMPAT 2 64 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 65 66 #elif defined(CONFIG_MPC8555) 67 #define CONFIG_MAX_CPUS 1 68 #define CONFIG_SYS_FSL_NUM_LAWS 8 69 #define CONFIG_SYS_FSL_SEC_COMPAT 2 70 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 71 72 #elif defined(CONFIG_MPC8560) 73 #define CONFIG_MAX_CPUS 1 74 #define CONFIG_SYS_FSL_NUM_LAWS 8 75 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 76 77 #elif defined(CONFIG_MPC8568) 78 #define CONFIG_MAX_CPUS 1 79 #define CONFIG_SYS_FSL_NUM_LAWS 10 80 #define CONFIG_SYS_FSL_SEC_COMPAT 2 81 #define QE_MURAM_SIZE 0x10000UL 82 #define MAX_QE_RISC 2 83 #define QE_NUM_OF_SNUM 28 84 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 85 86 #elif defined(CONFIG_MPC8569) 87 #define CONFIG_MAX_CPUS 1 88 #define CONFIG_SYS_FSL_NUM_LAWS 10 89 #define CONFIG_SYS_FSL_SEC_COMPAT 2 90 #define QE_MURAM_SIZE 0x20000UL 91 #define MAX_QE_RISC 4 92 #define QE_NUM_OF_SNUM 46 93 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 94 95 #elif defined(CONFIG_MPC8572) 96 #define CONFIG_MAX_CPUS 2 97 #define CONFIG_SYS_FSL_NUM_LAWS 12 98 #define CONFIG_SYS_FSL_SEC_COMPAT 2 99 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 100 #define CONFIG_SYS_FSL_ERRATUM_DDR_115 101 #define CONFIG_SYS_FSL_ERRATUM_DDR111_DDR134 102 103 #elif defined(CONFIG_P1010) 104 #define CONFIG_MAX_CPUS 1 105 #define CONFIG_FSL_SDHC_V2_3 106 #define CONFIG_SYS_FSL_NUM_LAWS 12 107 #define CONFIG_TSECV2 108 #define CONFIG_SYS_FSL_SEC_COMPAT 4 109 #define CONFIG_FSL_SATA_V2 110 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 111 #define CONFIG_NUM_DDR_CONTROLLERS 1 112 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 113 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2" 114 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY 115 #define CONFIG_SYS_FSL_ERRATUM_IFC_A002769 116 117 /* P1011 is single core version of P1020 */ 118 #elif defined(CONFIG_P1011) 119 #define CONFIG_MAX_CPUS 1 120 #define CONFIG_SYS_FSL_NUM_LAWS 12 121 #define CONFIG_TSECV2 122 #define CONFIG_FSL_PCIE_DISABLE_ASPM 123 #define CONFIG_SYS_FSL_SEC_COMPAT 2 124 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 125 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 126 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 127 128 /* P1012 is single core version of P1021 */ 129 #elif defined(CONFIG_P1012) 130 #define CONFIG_MAX_CPUS 1 131 #define CONFIG_SYS_FSL_NUM_LAWS 12 132 #define CONFIG_TSECV2 133 #define CONFIG_FSL_PCIE_DISABLE_ASPM 134 #define CONFIG_SYS_FSL_SEC_COMPAT 2 135 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 136 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 137 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 138 #define QE_MURAM_SIZE 0x6000UL 139 #define MAX_QE_RISC 1 140 #define QE_NUM_OF_SNUM 28 141 142 /* P1013 is single core version of P1022 */ 143 #elif defined(CONFIG_P1013) 144 #define CONFIG_MAX_CPUS 1 145 #define CONFIG_SYS_FSL_NUM_LAWS 12 146 #define CONFIG_TSECV2 147 #define CONFIG_SYS_FSL_SEC_COMPAT 2 148 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 149 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 150 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 151 #define CONFIG_FSL_SATA_ERRATUM_A001 152 153 #elif defined(CONFIG_P1014) 154 #define CONFIG_MAX_CPUS 1 155 #define CONFIG_FSL_SDHC_V2_3 156 #define CONFIG_SYS_FSL_NUM_LAWS 12 157 #define CONFIG_TSECV2 158 #define CONFIG_SYS_FSL_SEC_COMPAT 4 159 #define CONFIG_FSL_SATA_V2 160 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 161 #define CONFIG_NUM_DDR_CONTROLLERS 1 162 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 163 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY 164 #define CONFIG_SYS_FSL_ERRATUM_IFC_A002769 165 166 /* P1015 is single core version of P1024 */ 167 #elif defined(CONFIG_P1015) 168 #define CONFIG_MAX_CPUS 1 169 #define CONFIG_SYS_FSL_NUM_LAWS 12 170 #define CONFIG_TSECV2 171 #define CONFIG_FSL_PCIE_DISABLE_ASPM 172 #define CONFIG_SYS_FSL_SEC_COMPAT 2 173 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 174 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 175 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 176 177 /* P1016 is single core version of P1025 */ 178 #elif defined(CONFIG_P1016) 179 #define CONFIG_MAX_CPUS 1 180 #define CONFIG_SYS_FSL_NUM_LAWS 12 181 #define CONFIG_TSECV2 182 #define CONFIG_FSL_PCIE_DISABLE_ASPM 183 #define CONFIG_SYS_FSL_SEC_COMPAT 2 184 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 185 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 186 #define QE_MURAM_SIZE 0x6000UL 187 #define MAX_QE_RISC 1 188 #define QE_NUM_OF_SNUM 28 189 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 190 191 /* P1017 is single core version of P1023 */ 192 #elif defined(CONFIG_P1017) 193 #define CONFIG_MAX_CPUS 1 194 #define CONFIG_SYS_FSL_NUM_LAWS 12 195 #define CONFIG_SYS_FSL_SEC_COMPAT 4 196 #define CONFIG_SYS_NUM_FMAN 1 197 #define CONFIG_SYS_NUM_FM1_DTSEC 2 198 #define CONFIG_NUM_DDR_CONTROLLERS 1 199 #define CONFIG_SYS_QMAN_NUM_PORTALS 3 200 #define CONFIG_SYS_BMAN_NUM_PORTALS 3 201 #define CONFIG_SYS_FM_MURAM_SIZE 0x10000 202 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2" 203 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff600000 204 205 #elif defined(CONFIG_P1020) 206 #define CONFIG_MAX_CPUS 2 207 #define CONFIG_SYS_FSL_NUM_LAWS 12 208 #define CONFIG_TSECV2 209 #define CONFIG_FSL_PCIE_DISABLE_ASPM 210 #define CONFIG_SYS_FSL_SEC_COMPAT 2 211 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 212 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 213 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 214 215 #elif defined(CONFIG_P1021) 216 #define CONFIG_MAX_CPUS 2 217 #define CONFIG_SYS_FSL_NUM_LAWS 12 218 #define CONFIG_TSECV2 219 #define CONFIG_FSL_PCIE_DISABLE_ASPM 220 #define CONFIG_SYS_FSL_SEC_COMPAT 2 221 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 222 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 223 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 224 #define QE_MURAM_SIZE 0x6000UL 225 #define MAX_QE_RISC 1 226 #define QE_NUM_OF_SNUM 28 227 228 #elif defined(CONFIG_P1022) 229 #define CONFIG_MAX_CPUS 2 230 #define CONFIG_SYS_FSL_NUM_LAWS 12 231 #define CONFIG_TSECV2 232 #define CONFIG_SYS_FSL_SEC_COMPAT 2 233 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 234 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 235 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 236 #define CONFIG_FSL_SATA_ERRATUM_A001 237 238 #elif defined(CONFIG_P1023) 239 #define CONFIG_MAX_CPUS 2 240 #define CONFIG_SYS_FSL_NUM_LAWS 12 241 #define CONFIG_SYS_FSL_SEC_COMPAT 4 242 #define CONFIG_SYS_NUM_FMAN 1 243 #define CONFIG_SYS_NUM_FM1_DTSEC 2 244 #define CONFIG_NUM_DDR_CONTROLLERS 1 245 #define CONFIG_SYS_QMAN_NUM_PORTALS 3 246 #define CONFIG_SYS_BMAN_NUM_PORTALS 3 247 #define CONFIG_SYS_FM_MURAM_SIZE 0x10000 248 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2" 249 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff600000 250 251 /* P1024 is lower end variant of P1020 */ 252 #elif defined(CONFIG_P1024) 253 #define CONFIG_MAX_CPUS 2 254 #define CONFIG_SYS_FSL_NUM_LAWS 12 255 #define CONFIG_TSECV2 256 #define CONFIG_FSL_PCIE_DISABLE_ASPM 257 #define CONFIG_SYS_FSL_SEC_COMPAT 2 258 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 259 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 260 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 261 262 /* P1025 is lower end variant of P1021 */ 263 #elif defined(CONFIG_P1025) 264 #define CONFIG_MAX_CPUS 2 265 #define CONFIG_SYS_FSL_NUM_LAWS 12 266 #define CONFIG_TSECV2 267 #define CONFIG_FSL_PCIE_DISABLE_ASPM 268 #define CONFIG_SYS_FSL_SEC_COMPAT 2 269 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 270 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 271 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 272 #define QE_MURAM_SIZE 0x6000UL 273 #define MAX_QE_RISC 1 274 #define QE_NUM_OF_SNUM 28 275 276 /* P2010 is single core version of P2020 */ 277 #elif defined(CONFIG_P2010) 278 #define CONFIG_MAX_CPUS 1 279 #define CONFIG_SYS_FSL_NUM_LAWS 12 280 #define CONFIG_SYS_FSL_SEC_COMPAT 2 281 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 282 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 283 #define CONFIG_SYS_FSL_ERRATUM_ESDHC_A001 284 285 #elif defined(CONFIG_P2020) 286 #define CONFIG_MAX_CPUS 2 287 #define CONFIG_SYS_FSL_NUM_LAWS 12 288 #define CONFIG_SYS_FSL_SEC_COMPAT 2 289 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 290 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 291 #define CONFIG_SYS_FSL_ERRATUM_ESDHC_A001 292 293 #elif defined(CONFIG_PPC_P2040) 294 #define CONFIG_MAX_CPUS 4 295 #define CONFIG_SYS_FSL_NUM_CC_PLLS 2 296 #define CONFIG_SYS_FSL_NUM_LAWS 32 297 #define CONFIG_SYS_FSL_SEC_COMPAT 4 298 #define CONFIG_SYS_NUM_FMAN 1 299 #define CONFIG_SYS_NUM_FM1_DTSEC 5 300 #define CONFIG_NUM_DDR_CONTROLLERS 1 301 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000 302 #define CONFIG_SYS_FSL_TBCLK_DIV 32 303 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2" 304 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 305 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE 306 #define CONFIG_SYS_FSL_USB2_PHY_ENABLE 307 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY 308 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 309 310 #elif defined(CONFIG_PPC_P2041) 311 #define CONFIG_MAX_CPUS 4 312 #define CONFIG_SYS_FSL_NUM_CC_PLLS 2 313 #define CONFIG_SYS_FSL_NUM_LAWS 32 314 #define CONFIG_SYS_FSL_SEC_COMPAT 4 315 #define CONFIG_SYS_NUM_FMAN 1 316 #define CONFIG_SYS_NUM_FM1_DTSEC 5 317 #define CONFIG_SYS_NUM_FM1_10GEC 1 318 #define CONFIG_NUM_DDR_CONTROLLERS 1 319 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000 320 #define CONFIG_SYS_FSL_TBCLK_DIV 32 321 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2" 322 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 323 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE 324 #define CONFIG_SYS_FSL_USB2_PHY_ENABLE 325 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY 326 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 327 328 #elif defined(CONFIG_PPC_P3041) 329 #define CONFIG_MAX_CPUS 4 330 #define CONFIG_SYS_FSL_NUM_CC_PLLS 2 331 #define CONFIG_SYS_FSL_NUM_LAWS 32 332 #define CONFIG_SYS_FSL_SEC_COMPAT 4 333 #define CONFIG_SYS_NUM_FMAN 1 334 #define CONFIG_SYS_NUM_FM1_DTSEC 5 335 #define CONFIG_SYS_NUM_FM1_10GEC 1 336 #define CONFIG_NUM_DDR_CONTROLLERS 1 337 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000 338 #define CONFIG_SYS_FSL_TBCLK_DIV 32 339 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2" 340 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 341 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE 342 #define CONFIG_SYS_FSL_USB2_PHY_ENABLE 343 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY 344 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 345 346 #elif defined(CONFIG_PPC_P4040) 347 #define CONFIG_MAX_CPUS 4 348 #define CONFIG_SYS_FSL_NUM_CC_PLLS 4 349 #define CONFIG_SYS_FSL_NUM_LAWS 32 350 #define CONFIG_SYS_FSL_SEC_COMPAT 4 351 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000 352 #define CONFIG_SYS_FSL_TBCLK_DIV 16 353 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,p4080-pcie" 354 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 355 356 #elif defined(CONFIG_PPC_P4080) 357 #define CONFIG_MAX_CPUS 8 358 #define CONFIG_SYS_FSL_NUM_CC_PLLS 4 359 #define CONFIG_SYS_FSL_NUM_LAWS 32 360 #define CONFIG_SYS_FSL_SEC_COMPAT 4 361 #define CONFIG_SYS_NUM_FMAN 2 362 #define CONFIG_SYS_NUM_FM1_DTSEC 4 363 #define CONFIG_SYS_NUM_FM2_DTSEC 4 364 #define CONFIG_SYS_NUM_FM1_10GEC 1 365 #define CONFIG_SYS_NUM_FM2_10GEC 1 366 #define CONFIG_NUM_DDR_CONTROLLERS 2 367 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000 368 #define CONFIG_SYS_FSL_TBCLK_DIV 16 369 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,p4080-pcie" 370 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 371 #define CONFIG_SYS_FSL_ERRATUM_CPC_A002 372 #define CONFIG_SYS_FSL_ERRATUM_CPC_A003 373 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003 374 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 375 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 376 #define CONFIG_SYS_FSL_ERRATUM_ESDHC135 377 #define CONFIG_SYS_FSL_ERRATUM_ESDHC136 378 #define CONFIG_SYS_P4080_ERRATUM_CPU22 379 #define CONFIG_SYS_P4080_ERRATUM_SERDES8 380 #define CONFIG_SYS_P4080_ERRATUM_SERDES9 381 #define CONFIG_SYS_P4080_ERRATUM_SERDES_A001 382 #define CONFIG_SYS_P4080_ERRATUM_SERDES_A005 383 384 /* P5010 is single core version of P5020 */ 385 #elif defined(CONFIG_PPC_P5010) 386 #define CONFIG_MAX_CPUS 1 387 #define CONFIG_SYS_FSL_NUM_CC_PLLS 2 388 #define CONFIG_SYS_FSL_NUM_LAWS 32 389 #define CONFIG_SYS_FSL_SEC_COMPAT 4 390 #define CONFIG_SYS_NUM_FMAN 1 391 #define CONFIG_SYS_NUM_FM1_DTSEC 5 392 #define CONFIG_SYS_NUM_FM1_10GEC 1 393 #define CONFIG_NUM_DDR_CONTROLLERS 1 394 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000 395 #define CONFIG_SYS_FSL_TBCLK_DIV 32 396 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2" 397 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 398 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE 399 #define CONFIG_SYS_FSL_USB2_PHY_ENABLE 400 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY 401 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 402 403 #elif defined(CONFIG_PPC_P5020) 404 #define CONFIG_MAX_CPUS 2 405 #define CONFIG_SYS_FSL_NUM_CC_PLLS 2 406 #define CONFIG_SYS_FSL_NUM_LAWS 32 407 #define CONFIG_SYS_FSL_SEC_COMPAT 4 408 #define CONFIG_SYS_NUM_FMAN 1 409 #define CONFIG_SYS_NUM_FM1_DTSEC 5 410 #define CONFIG_SYS_NUM_FM1_10GEC 1 411 #define CONFIG_NUM_DDR_CONTROLLERS 2 412 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000 413 #define CONFIG_SYS_FSL_TBCLK_DIV 32 414 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2" 415 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 416 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE 417 #define CONFIG_SYS_FSL_USB2_PHY_ENABLE 418 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY 419 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 420 421 #else 422 #error Processor type not defined for this platform 423 #endif 424 425 #ifndef CONFIG_SYS_CCSRBAR_DEFAULT 426 #error "CONFIG_SYS_CCSRBAR_DEFAULT is not defined for this platform." 427 #endif 428 429 #endif /* _ASM_MPC85xx_CONFIG_H_ */ 430