1 /* 2 * Copyright 2011 Freescale Semiconductor, Inc. 3 * 4 * This program is free software; you can redistribute it and/or 5 * modify it under the terms of the GNU General Public License as 6 * published by the Free Software Foundation; either version 2 of 7 * the License, or (at your option) any later version. 8 * 9 * This program is distributed in the hope that it will be useful, 10 * but WITHOUT ANY WARRANTY; without even the implied warranty of 11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 * GNU General Public License for more details. 13 * 14 * You should have received a copy of the GNU General Public License 15 * along with this program; if not, write to the Free Software 16 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 17 * MA 02111-1307 USA 18 * 19 */ 20 21 #ifndef _ASM_MPC85xx_CONFIG_H_ 22 #define _ASM_MPC85xx_CONFIG_H_ 23 24 /* SoC specific defines for Freescale MPC85xx (PQ3) and QorIQ processors */ 25 26 #ifdef CONFIG_SYS_CCSRBAR_DEFAULT 27 #error "Do not define CONFIG_SYS_CCSRBAR_DEFAULT in the board header file." 28 #endif 29 30 /* Number of TLB CAM entries we have on FSL Book-E chips */ 31 #if defined(CONFIG_E500MC) 32 #define CONFIG_SYS_NUM_TLBCAMS 64 33 #elif defined(CONFIG_E500) 34 #define CONFIG_SYS_NUM_TLBCAMS 16 35 #endif 36 37 #if defined(CONFIG_MPC8536) 38 #define CONFIG_MAX_CPUS 1 39 #define CONFIG_SYS_FSL_NUM_LAWS 12 40 #define CONFIG_SYS_FSL_SEC_COMPAT 2 41 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 42 43 #elif defined(CONFIG_MPC8540) 44 #define CONFIG_MAX_CPUS 1 45 #define CONFIG_SYS_FSL_NUM_LAWS 8 46 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 47 48 #elif defined(CONFIG_MPC8541) 49 #define CONFIG_MAX_CPUS 1 50 #define CONFIG_SYS_FSL_NUM_LAWS 8 51 #define CONFIG_SYS_FSL_SEC_COMPAT 2 52 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 53 54 #elif defined(CONFIG_MPC8544) 55 #define CONFIG_MAX_CPUS 1 56 #define CONFIG_SYS_FSL_NUM_LAWS 10 57 #define CONFIG_SYS_FSL_SEC_COMPAT 2 58 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 59 60 #elif defined(CONFIG_MPC8548) 61 #define CONFIG_MAX_CPUS 1 62 #define CONFIG_SYS_FSL_NUM_LAWS 10 63 #define CONFIG_SYS_FSL_SEC_COMPAT 2 64 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 65 66 #elif defined(CONFIG_MPC8555) 67 #define CONFIG_MAX_CPUS 1 68 #define CONFIG_SYS_FSL_NUM_LAWS 8 69 #define CONFIG_SYS_FSL_SEC_COMPAT 2 70 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 71 72 #elif defined(CONFIG_MPC8560) 73 #define CONFIG_MAX_CPUS 1 74 #define CONFIG_SYS_FSL_NUM_LAWS 8 75 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 76 77 #elif defined(CONFIG_MPC8568) 78 #define CONFIG_MAX_CPUS 1 79 #define CONFIG_SYS_FSL_NUM_LAWS 10 80 #define CONFIG_SYS_FSL_SEC_COMPAT 2 81 #define QE_MURAM_SIZE 0x10000UL 82 #define MAX_QE_RISC 2 83 #define QE_NUM_OF_SNUM 28 84 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 85 86 #elif defined(CONFIG_MPC8569) 87 #define CONFIG_MAX_CPUS 1 88 #define CONFIG_SYS_FSL_NUM_LAWS 10 89 #define CONFIG_SYS_FSL_SEC_COMPAT 2 90 #define QE_MURAM_SIZE 0x20000UL 91 #define MAX_QE_RISC 4 92 #define QE_NUM_OF_SNUM 46 93 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 94 95 #elif defined(CONFIG_MPC8572) 96 #define CONFIG_MAX_CPUS 2 97 #define CONFIG_SYS_FSL_NUM_LAWS 12 98 #define CONFIG_SYS_FSL_SEC_COMPAT 2 99 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 100 #define CONFIG_SYS_FSL_ERRATUM_DDR_115 101 #define CONFIG_SYS_FSL_ERRATUM_DDR111_DDR134 102 103 #elif defined(CONFIG_P1010) 104 #define CONFIG_MAX_CPUS 1 105 #define CONFIG_FSL_SDHC_V2_3 106 #define CONFIG_SYS_FSL_NUM_LAWS 12 107 #define CONFIG_TSECV2 108 #define CONFIG_SYS_FSL_SEC_COMPAT 4 109 #define CONFIG_FSL_SATA_V2 110 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 111 #define CONFIG_NUM_DDR_CONTROLLERS 1 112 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 113 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2" 114 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY 115 #define CONFIG_SYS_FSL_ERRATUM_IFC_A002769 116 #define CONFIG_SYS_FSL_ERRATUM_P1010_A003549 117 118 /* P1011 is single core version of P1020 */ 119 #elif defined(CONFIG_P1011) 120 #define CONFIG_MAX_CPUS 1 121 #define CONFIG_SYS_FSL_NUM_LAWS 12 122 #define CONFIG_TSECV2 123 #define CONFIG_FSL_PCIE_DISABLE_ASPM 124 #define CONFIG_SYS_FSL_SEC_COMPAT 2 125 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 126 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 127 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 128 129 /* P1012 is single core version of P1021 */ 130 #elif defined(CONFIG_P1012) 131 #define CONFIG_MAX_CPUS 1 132 #define CONFIG_SYS_FSL_NUM_LAWS 12 133 #define CONFIG_TSECV2 134 #define CONFIG_FSL_PCIE_DISABLE_ASPM 135 #define CONFIG_SYS_FSL_SEC_COMPAT 2 136 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 137 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 138 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 139 #define QE_MURAM_SIZE 0x6000UL 140 #define MAX_QE_RISC 1 141 #define QE_NUM_OF_SNUM 28 142 143 /* P1013 is single core version of P1022 */ 144 #elif defined(CONFIG_P1013) 145 #define CONFIG_MAX_CPUS 1 146 #define CONFIG_SYS_FSL_NUM_LAWS 12 147 #define CONFIG_TSECV2 148 #define CONFIG_SYS_FSL_SEC_COMPAT 2 149 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 150 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 151 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 152 #define CONFIG_FSL_SATA_ERRATUM_A001 153 154 #elif defined(CONFIG_P1014) 155 #define CONFIG_MAX_CPUS 1 156 #define CONFIG_FSL_SDHC_V2_3 157 #define CONFIG_SYS_FSL_NUM_LAWS 12 158 #define CONFIG_TSECV2 159 #define CONFIG_SYS_FSL_SEC_COMPAT 4 160 #define CONFIG_FSL_SATA_V2 161 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 162 #define CONFIG_NUM_DDR_CONTROLLERS 1 163 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 164 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY 165 #define CONFIG_SYS_FSL_ERRATUM_IFC_A002769 166 #define CONFIG_SYS_FSL_ERRATUM_P1010_A003549 167 168 /* P1015 is single core version of P1024 */ 169 #elif defined(CONFIG_P1015) 170 #define CONFIG_MAX_CPUS 1 171 #define CONFIG_SYS_FSL_NUM_LAWS 12 172 #define CONFIG_TSECV2 173 #define CONFIG_FSL_PCIE_DISABLE_ASPM 174 #define CONFIG_SYS_FSL_SEC_COMPAT 2 175 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 176 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 177 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 178 179 /* P1016 is single core version of P1025 */ 180 #elif defined(CONFIG_P1016) 181 #define CONFIG_MAX_CPUS 1 182 #define CONFIG_SYS_FSL_NUM_LAWS 12 183 #define CONFIG_TSECV2 184 #define CONFIG_FSL_PCIE_DISABLE_ASPM 185 #define CONFIG_SYS_FSL_SEC_COMPAT 2 186 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 187 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 188 #define QE_MURAM_SIZE 0x6000UL 189 #define MAX_QE_RISC 1 190 #define QE_NUM_OF_SNUM 28 191 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 192 193 /* P1017 is single core version of P1023 */ 194 #elif defined(CONFIG_P1017) 195 #define CONFIG_MAX_CPUS 1 196 #define CONFIG_SYS_FSL_NUM_LAWS 12 197 #define CONFIG_SYS_FSL_SEC_COMPAT 4 198 #define CONFIG_SYS_NUM_FMAN 1 199 #define CONFIG_SYS_NUM_FM1_DTSEC 2 200 #define CONFIG_NUM_DDR_CONTROLLERS 1 201 #define CONFIG_SYS_QMAN_NUM_PORTALS 3 202 #define CONFIG_SYS_BMAN_NUM_PORTALS 3 203 #define CONFIG_SYS_FM_MURAM_SIZE 0x10000 204 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2" 205 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff600000 206 207 #elif defined(CONFIG_P1020) 208 #define CONFIG_MAX_CPUS 2 209 #define CONFIG_SYS_FSL_NUM_LAWS 12 210 #define CONFIG_TSECV2 211 #define CONFIG_FSL_PCIE_DISABLE_ASPM 212 #define CONFIG_SYS_FSL_SEC_COMPAT 2 213 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 214 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 215 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 216 217 #elif defined(CONFIG_P1021) 218 #define CONFIG_MAX_CPUS 2 219 #define CONFIG_SYS_FSL_NUM_LAWS 12 220 #define CONFIG_TSECV2 221 #define CONFIG_FSL_PCIE_DISABLE_ASPM 222 #define CONFIG_SYS_FSL_SEC_COMPAT 2 223 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 224 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 225 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 226 #define QE_MURAM_SIZE 0x6000UL 227 #define MAX_QE_RISC 1 228 #define QE_NUM_OF_SNUM 28 229 230 #elif defined(CONFIG_P1022) 231 #define CONFIG_MAX_CPUS 2 232 #define CONFIG_SYS_FSL_NUM_LAWS 12 233 #define CONFIG_TSECV2 234 #define CONFIG_SYS_FSL_SEC_COMPAT 2 235 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 236 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 237 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 238 #define CONFIG_FSL_SATA_ERRATUM_A001 239 240 #elif defined(CONFIG_P1023) 241 #define CONFIG_MAX_CPUS 2 242 #define CONFIG_SYS_FSL_NUM_LAWS 12 243 #define CONFIG_SYS_FSL_SEC_COMPAT 4 244 #define CONFIG_SYS_NUM_FMAN 1 245 #define CONFIG_SYS_NUM_FM1_DTSEC 2 246 #define CONFIG_NUM_DDR_CONTROLLERS 1 247 #define CONFIG_SYS_QMAN_NUM_PORTALS 3 248 #define CONFIG_SYS_BMAN_NUM_PORTALS 3 249 #define CONFIG_SYS_FM_MURAM_SIZE 0x10000 250 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2" 251 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff600000 252 253 /* P1024 is lower end variant of P1020 */ 254 #elif defined(CONFIG_P1024) 255 #define CONFIG_MAX_CPUS 2 256 #define CONFIG_SYS_FSL_NUM_LAWS 12 257 #define CONFIG_TSECV2 258 #define CONFIG_FSL_PCIE_DISABLE_ASPM 259 #define CONFIG_SYS_FSL_SEC_COMPAT 2 260 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 261 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 262 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 263 264 /* P1025 is lower end variant of P1021 */ 265 #elif defined(CONFIG_P1025) 266 #define CONFIG_MAX_CPUS 2 267 #define CONFIG_SYS_FSL_NUM_LAWS 12 268 #define CONFIG_TSECV2 269 #define CONFIG_FSL_PCIE_DISABLE_ASPM 270 #define CONFIG_SYS_FSL_SEC_COMPAT 2 271 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 272 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 273 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 274 #define QE_MURAM_SIZE 0x6000UL 275 #define MAX_QE_RISC 1 276 #define QE_NUM_OF_SNUM 28 277 278 /* P2010 is single core version of P2020 */ 279 #elif defined(CONFIG_P2010) 280 #define CONFIG_MAX_CPUS 1 281 #define CONFIG_SYS_FSL_NUM_LAWS 12 282 #define CONFIG_SYS_FSL_SEC_COMPAT 2 283 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 284 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 285 #define CONFIG_SYS_FSL_ERRATUM_ESDHC_A001 286 287 #elif defined(CONFIG_P2020) 288 #define CONFIG_MAX_CPUS 2 289 #define CONFIG_SYS_FSL_NUM_LAWS 12 290 #define CONFIG_SYS_FSL_SEC_COMPAT 2 291 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 292 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 293 #define CONFIG_SYS_FSL_ERRATUM_ESDHC_A001 294 295 #elif defined(CONFIG_PPC_P2040) 296 #define CONFIG_MAX_CPUS 4 297 #define CONFIG_SYS_FSL_NUM_CC_PLLS 2 298 #define CONFIG_SYS_FSL_NUM_LAWS 32 299 #define CONFIG_SYS_FSL_SEC_COMPAT 4 300 #define CONFIG_SYS_NUM_FMAN 1 301 #define CONFIG_SYS_NUM_FM1_DTSEC 5 302 #define CONFIG_NUM_DDR_CONTROLLERS 1 303 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000 304 #define CONFIG_SYS_FSL_TBCLK_DIV 32 305 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2" 306 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 307 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE 308 #define CONFIG_SYS_FSL_USB2_PHY_ENABLE 309 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY 310 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 311 312 #elif defined(CONFIG_PPC_P2041) 313 #define CONFIG_MAX_CPUS 4 314 #define CONFIG_SYS_FSL_NUM_CC_PLLS 2 315 #define CONFIG_SYS_FSL_NUM_LAWS 32 316 #define CONFIG_SYS_FSL_SEC_COMPAT 4 317 #define CONFIG_SYS_NUM_FMAN 1 318 #define CONFIG_SYS_NUM_FM1_DTSEC 5 319 #define CONFIG_SYS_NUM_FM1_10GEC 1 320 #define CONFIG_NUM_DDR_CONTROLLERS 1 321 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000 322 #define CONFIG_SYS_FSL_TBCLK_DIV 32 323 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2" 324 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 325 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE 326 #define CONFIG_SYS_FSL_USB2_PHY_ENABLE 327 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY 328 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 329 330 #elif defined(CONFIG_PPC_P3041) 331 #define CONFIG_MAX_CPUS 4 332 #define CONFIG_SYS_FSL_NUM_CC_PLLS 2 333 #define CONFIG_SYS_FSL_NUM_LAWS 32 334 #define CONFIG_SYS_FSL_SEC_COMPAT 4 335 #define CONFIG_SYS_NUM_FMAN 1 336 #define CONFIG_SYS_NUM_FM1_DTSEC 5 337 #define CONFIG_SYS_NUM_FM1_10GEC 1 338 #define CONFIG_NUM_DDR_CONTROLLERS 1 339 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000 340 #define CONFIG_SYS_FSL_TBCLK_DIV 32 341 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2" 342 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 343 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE 344 #define CONFIG_SYS_FSL_USB2_PHY_ENABLE 345 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY 346 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 347 348 #elif defined(CONFIG_PPC_P4040) 349 #define CONFIG_MAX_CPUS 4 350 #define CONFIG_SYS_FSL_NUM_CC_PLLS 4 351 #define CONFIG_SYS_FSL_NUM_LAWS 32 352 #define CONFIG_SYS_FSL_SEC_COMPAT 4 353 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000 354 #define CONFIG_SYS_FSL_TBCLK_DIV 16 355 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,p4080-pcie" 356 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 357 358 #elif defined(CONFIG_PPC_P4080) 359 #define CONFIG_MAX_CPUS 8 360 #define CONFIG_SYS_FSL_NUM_CC_PLLS 4 361 #define CONFIG_SYS_FSL_NUM_LAWS 32 362 #define CONFIG_SYS_FSL_SEC_COMPAT 4 363 #define CONFIG_SYS_NUM_FMAN 2 364 #define CONFIG_SYS_NUM_FM1_DTSEC 4 365 #define CONFIG_SYS_NUM_FM2_DTSEC 4 366 #define CONFIG_SYS_NUM_FM1_10GEC 1 367 #define CONFIG_SYS_NUM_FM2_10GEC 1 368 #define CONFIG_NUM_DDR_CONTROLLERS 2 369 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000 370 #define CONFIG_SYS_FSL_TBCLK_DIV 16 371 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,p4080-pcie" 372 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 373 #define CONFIG_SYS_FSL_ERRATUM_CPC_A002 374 #define CONFIG_SYS_FSL_ERRATUM_CPC_A003 375 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003 376 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 377 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 378 #define CONFIG_SYS_FSL_ERRATUM_ESDHC135 379 #define CONFIG_SYS_FSL_ERRATUM_ESDHC136 380 #define CONFIG_SYS_P4080_ERRATUM_CPU22 381 #define CONFIG_SYS_P4080_ERRATUM_SERDES8 382 #define CONFIG_SYS_P4080_ERRATUM_SERDES9 383 #define CONFIG_SYS_P4080_ERRATUM_SERDES_A001 384 #define CONFIG_SYS_P4080_ERRATUM_SERDES_A005 385 386 /* P5010 is single core version of P5020 */ 387 #elif defined(CONFIG_PPC_P5010) 388 #define CONFIG_MAX_CPUS 1 389 #define CONFIG_SYS_FSL_NUM_CC_PLLS 2 390 #define CONFIG_SYS_FSL_NUM_LAWS 32 391 #define CONFIG_SYS_FSL_SEC_COMPAT 4 392 #define CONFIG_SYS_NUM_FMAN 1 393 #define CONFIG_SYS_NUM_FM1_DTSEC 5 394 #define CONFIG_SYS_NUM_FM1_10GEC 1 395 #define CONFIG_NUM_DDR_CONTROLLERS 1 396 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000 397 #define CONFIG_SYS_FSL_TBCLK_DIV 32 398 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2" 399 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 400 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE 401 #define CONFIG_SYS_FSL_USB2_PHY_ENABLE 402 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY 403 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 404 405 #elif defined(CONFIG_PPC_P5020) 406 #define CONFIG_MAX_CPUS 2 407 #define CONFIG_SYS_FSL_NUM_CC_PLLS 2 408 #define CONFIG_SYS_FSL_NUM_LAWS 32 409 #define CONFIG_SYS_FSL_SEC_COMPAT 4 410 #define CONFIG_SYS_NUM_FMAN 1 411 #define CONFIG_SYS_NUM_FM1_DTSEC 5 412 #define CONFIG_SYS_NUM_FM1_10GEC 1 413 #define CONFIG_NUM_DDR_CONTROLLERS 2 414 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000 415 #define CONFIG_SYS_FSL_TBCLK_DIV 32 416 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2" 417 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 418 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE 419 #define CONFIG_SYS_FSL_USB2_PHY_ENABLE 420 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY 421 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 422 423 #else 424 #error Processor type not defined for this platform 425 #endif 426 427 #ifndef CONFIG_SYS_CCSRBAR_DEFAULT 428 #error "CONFIG_SYS_CCSRBAR_DEFAULT is not defined for this platform." 429 #endif 430 431 #endif /* _ASM_MPC85xx_CONFIG_H_ */ 432