1 /* 2 * Copyright 2004,2007-2011 Freescale Semiconductor, Inc. 3 * (C) Copyright 2002, 2003 Motorola Inc. 4 * Xianghua Xiao (X.Xiao@motorola.com) 5 * 6 * (C) Copyright 2000 7 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 8 * 9 * See file CREDITS for list of people who contributed to this 10 * project. 11 * 12 * This program is free software; you can redistribute it and/or 13 * modify it under the terms of the GNU General Public License as 14 * published by the Free Software Foundation; either version 2 of 15 * the License, or (at your option) any later version. 16 * 17 * This program is distributed in the hope that it will be useful, 18 * but WITHOUT ANY WARRANTY; without even the implied warranty of 19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 20 * GNU General Public License for more details. 21 * 22 * You should have received a copy of the GNU General Public License 23 * along with this program; if not, write to the Free Software 24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 25 * MA 02111-1307 USA 26 */ 27 28 #include <config.h> 29 #include <common.h> 30 #include <watchdog.h> 31 #include <command.h> 32 #include <fsl_esdhc.h> 33 #include <asm/cache.h> 34 #include <asm/io.h> 35 #include <asm/mmu.h> 36 #include <asm/fsl_ifc.h> 37 #include <asm/fsl_law.h> 38 #include <asm/fsl_lbc.h> 39 #include <post.h> 40 #include <asm/processor.h> 41 #include <asm/fsl_ddr_sdram.h> 42 43 DECLARE_GLOBAL_DATA_PTR; 44 45 int checkcpu (void) 46 { 47 sys_info_t sysinfo; 48 uint pvr, svr; 49 uint ver; 50 uint major, minor; 51 struct cpu_type *cpu; 52 char buf1[32], buf2[32]; 53 #if defined(CONFIG_DDR_CLK_FREQ) || defined(CONFIG_FSL_CORENET) 54 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 55 #endif /* CONFIG_FSL_CORENET */ 56 #ifdef CONFIG_DDR_CLK_FREQ 57 u32 ddr_ratio = ((gur->porpllsr) & MPC85xx_PORPLLSR_DDR_RATIO) 58 >> MPC85xx_PORPLLSR_DDR_RATIO_SHIFT; 59 #else 60 #ifdef CONFIG_FSL_CORENET 61 u32 ddr_sync = ((gur->rcwsr[5]) & FSL_CORENET_RCWSR5_DDR_SYNC) 62 >> FSL_CORENET_RCWSR5_DDR_SYNC_SHIFT; 63 #else 64 u32 ddr_ratio = 0; 65 #endif /* CONFIG_FSL_CORENET */ 66 #endif /* CONFIG_DDR_CLK_FREQ */ 67 unsigned int i, core, nr_cores = cpu_numcores(); 68 u32 mask = cpu_mask(); 69 70 svr = get_svr(); 71 major = SVR_MAJ(svr); 72 #ifdef CONFIG_MPC8536 73 major &= 0x7; /* the msb of this nibble is a mfg code */ 74 #endif 75 minor = SVR_MIN(svr); 76 77 if (cpu_numcores() > 1) { 78 #ifndef CONFIG_MP 79 puts("Unicore software on multiprocessor system!!\n" 80 "To enable mutlticore build define CONFIG_MP\n"); 81 #endif 82 volatile ccsr_pic_t *pic = (void *)(CONFIG_SYS_MPC8xxx_PIC_ADDR); 83 printf("CPU%d: ", pic->whoami); 84 } else { 85 puts("CPU: "); 86 } 87 88 cpu = gd->cpu; 89 90 puts(cpu->name); 91 if (IS_E_PROCESSOR(svr)) 92 puts("E"); 93 94 printf(", Version: %d.%d, (0x%08x)\n", major, minor, svr); 95 96 pvr = get_pvr(); 97 ver = PVR_VER(pvr); 98 major = PVR_MAJ(pvr); 99 minor = PVR_MIN(pvr); 100 101 printf("Core: "); 102 switch(ver) { 103 case PVR_VER_E500_V1: 104 case PVR_VER_E500_V2: 105 puts("E500"); 106 break; 107 case PVR_VER_E500MC: 108 puts("E500MC"); 109 break; 110 case PVR_VER_E5500: 111 puts("E5500"); 112 break; 113 default: 114 puts("Unknown"); 115 break; 116 } 117 118 printf(", Version: %d.%d, (0x%08x)\n", major, minor, pvr); 119 120 get_sys_info(&sysinfo); 121 122 puts("Clock Configuration:"); 123 for_each_cpu(i, core, nr_cores, mask) { 124 if (!(i & 3)) 125 printf ("\n "); 126 printf("CPU%d:%-4s MHz, ", core, 127 strmhz(buf1, sysinfo.freqProcessor[core])); 128 } 129 printf("\n CCB:%-4s MHz,\n", strmhz(buf1, sysinfo.freqSystemBus)); 130 131 #ifdef CONFIG_FSL_CORENET 132 if (ddr_sync == 1) { 133 printf(" DDR:%-4s MHz (%s MT/s data rate) " 134 "(Synchronous), ", 135 strmhz(buf1, sysinfo.freqDDRBus/2), 136 strmhz(buf2, sysinfo.freqDDRBus)); 137 } else { 138 printf(" DDR:%-4s MHz (%s MT/s data rate) " 139 "(Asynchronous), ", 140 strmhz(buf1, sysinfo.freqDDRBus/2), 141 strmhz(buf2, sysinfo.freqDDRBus)); 142 } 143 #else 144 switch (ddr_ratio) { 145 case 0x0: 146 printf(" DDR:%-4s MHz (%s MT/s data rate), ", 147 strmhz(buf1, sysinfo.freqDDRBus/2), 148 strmhz(buf2, sysinfo.freqDDRBus)); 149 break; 150 case 0x7: 151 printf(" DDR:%-4s MHz (%s MT/s data rate) " 152 "(Synchronous), ", 153 strmhz(buf1, sysinfo.freqDDRBus/2), 154 strmhz(buf2, sysinfo.freqDDRBus)); 155 break; 156 default: 157 printf(" DDR:%-4s MHz (%s MT/s data rate) " 158 "(Asynchronous), ", 159 strmhz(buf1, sysinfo.freqDDRBus/2), 160 strmhz(buf2, sysinfo.freqDDRBus)); 161 break; 162 } 163 #endif 164 165 #if defined(CONFIG_FSL_LBC) 166 if (sysinfo.freqLocalBus > LCRR_CLKDIV) { 167 printf("LBC:%-4s MHz\n", strmhz(buf1, sysinfo.freqLocalBus)); 168 } else { 169 printf("LBC: unknown (LCRR[CLKDIV] = 0x%02lx)\n", 170 sysinfo.freqLocalBus); 171 } 172 #endif 173 174 #ifdef CONFIG_CPM2 175 printf("CPM: %s MHz\n", strmhz(buf1, sysinfo.freqSystemBus)); 176 #endif 177 178 #ifdef CONFIG_QE 179 printf(" QE:%-4s MHz\n", strmhz(buf1, sysinfo.freqQE)); 180 #endif 181 182 #ifdef CONFIG_SYS_DPAA_FMAN 183 for (i = 0; i < CONFIG_SYS_NUM_FMAN; i++) { 184 printf(" FMAN%d: %s MHz\n", i + 1, 185 strmhz(buf1, sysinfo.freqFMan[i])); 186 } 187 #endif 188 189 #ifdef CONFIG_SYS_DPAA_PME 190 printf(" PME: %s MHz\n", strmhz(buf1, sysinfo.freqPME)); 191 #endif 192 193 puts("L1: D-cache 32 kB enabled\n I-cache 32 kB enabled\n"); 194 195 return 0; 196 } 197 198 199 /* ------------------------------------------------------------------------- */ 200 201 int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) 202 { 203 /* Everything after the first generation of PQ3 parts has RSTCR */ 204 #if defined(CONFIG_MPC8540) || defined(CONFIG_MPC8541) || \ 205 defined(CONFIG_MPC8555) || defined(CONFIG_MPC8560) 206 unsigned long val, msr; 207 208 /* 209 * Initiate hard reset in debug control register DBCR0 210 * Make sure MSR[DE] = 1. This only resets the core. 211 */ 212 msr = mfmsr (); 213 msr |= MSR_DE; 214 mtmsr (msr); 215 216 val = mfspr(DBCR0); 217 val |= 0x70000000; 218 mtspr(DBCR0,val); 219 #else 220 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 221 out_be32(&gur->rstcr, 0x2); /* HRESET_REQ */ 222 udelay(100); 223 #endif 224 225 return 1; 226 } 227 228 229 /* 230 * Get timebase clock frequency 231 */ 232 #ifndef CONFIG_SYS_FSL_TBCLK_DIV 233 #define CONFIG_SYS_FSL_TBCLK_DIV 8 234 #endif 235 unsigned long get_tbclk (void) 236 { 237 unsigned long tbclk_div = CONFIG_SYS_FSL_TBCLK_DIV; 238 239 return (gd->bus_clk + (tbclk_div >> 1)) / tbclk_div; 240 } 241 242 243 #if defined(CONFIG_WATCHDOG) 244 void 245 watchdog_reset(void) 246 { 247 int re_enable = disable_interrupts(); 248 reset_85xx_watchdog(); 249 if (re_enable) enable_interrupts(); 250 } 251 252 void 253 reset_85xx_watchdog(void) 254 { 255 /* 256 * Clear TSR(WIS) bit by writing 1 257 */ 258 unsigned long val; 259 val = mfspr(SPRN_TSR); 260 val |= TSR_WIS; 261 mtspr(SPRN_TSR, val); 262 } 263 #endif /* CONFIG_WATCHDOG */ 264 265 /* 266 * Initializes on-chip MMC controllers. 267 * to override, implement board_mmc_init() 268 */ 269 int cpu_mmc_init(bd_t *bis) 270 { 271 #ifdef CONFIG_FSL_ESDHC 272 return fsl_esdhc_mmc_init(bis); 273 #else 274 return 0; 275 #endif 276 } 277 278 /* 279 * Print out the state of various machine registers. 280 * Currently prints out LAWs, BR0/OR0 for LBC, CSPR/CSOR/Timing 281 * parameters for IFC and TLBs 282 */ 283 void mpc85xx_reginfo(void) 284 { 285 print_tlbcam(); 286 print_laws(); 287 #if defined(CONFIG_FSL_LBC) 288 print_lbc_regs(); 289 #endif 290 #ifdef CONFIG_FSL_IFC 291 print_ifc_regs(); 292 #endif 293 294 } 295 296 /* Common ddr init for non-corenet fsl 85xx platforms */ 297 #ifndef CONFIG_FSL_CORENET 298 #if defined(CONFIG_SYS_RAMBOOT) && !defined(CONFIG_SYS_INIT_L2_ADDR) 299 phys_size_t initdram(int board_type) 300 { 301 #if defined(CONFIG_SPD_EEPROM) || defined(CONFIG_DDR_SPD) 302 return fsl_ddr_sdram_size(); 303 #else 304 return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024; 305 #endif 306 } 307 #else /* CONFIG_SYS_RAMBOOT */ 308 phys_size_t initdram(int board_type) 309 { 310 phys_size_t dram_size = 0; 311 312 #if defined(CONFIG_SYS_FSL_ERRATUM_DDR_MSYNC_IN) 313 { 314 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 315 unsigned int x = 10; 316 unsigned int i; 317 318 /* 319 * Work around to stabilize DDR DLL 320 */ 321 out_be32(&gur->ddrdllcr, 0x81000000); 322 asm("sync;isync;msync"); 323 udelay(200); 324 while (in_be32(&gur->ddrdllcr) != 0x81000100) { 325 setbits_be32(&gur->devdisr, 0x00010000); 326 for (i = 0; i < x; i++) 327 ; 328 clrbits_be32(&gur->devdisr, 0x00010000); 329 x++; 330 } 331 } 332 #endif 333 334 #if defined(CONFIG_SPD_EEPROM) || \ 335 defined(CONFIG_DDR_SPD) || \ 336 defined(CONFIG_SYS_DDR_RAW_TIMING) 337 dram_size = fsl_ddr_sdram(); 338 #else 339 dram_size = fixed_sdram(); 340 #endif 341 dram_size = setup_ddr_tlbs(dram_size / 0x100000); 342 dram_size *= 0x100000; 343 344 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) 345 /* 346 * Initialize and enable DDR ECC. 347 */ 348 ddr_enable_ecc(dram_size); 349 #endif 350 351 #if defined(CONFIG_FSL_LBC) 352 /* Some boards also have sdram on the lbc */ 353 lbc_sdram_init(); 354 #endif 355 356 debug("DDR: "); 357 return dram_size; 358 } 359 #endif /* CONFIG_SYS_RAMBOOT */ 360 #endif 361 362 #if CONFIG_POST & CONFIG_SYS_POST_MEMORY 363 364 /* Board-specific functions defined in each board's ddr.c */ 365 void fsl_ddr_get_spd(generic_spd_eeprom_t *ctrl_dimms_spd, 366 unsigned int ctrl_num); 367 void read_tlbcam_entry(int idx, u32 *valid, u32 *tsize, unsigned long *epn, 368 phys_addr_t *rpn); 369 unsigned int 370 setup_ddr_tlbs_phys(phys_addr_t p_addr, unsigned int memsize_in_meg); 371 372 void clear_ddr_tlbs_phys(phys_addr_t p_addr, unsigned int memsize_in_meg); 373 374 static void dump_spd_ddr_reg(void) 375 { 376 int i, j, k, m; 377 u8 *p_8; 378 u32 *p_32; 379 ccsr_ddr_t *ddr[CONFIG_NUM_DDR_CONTROLLERS]; 380 generic_spd_eeprom_t 381 spd[CONFIG_NUM_DDR_CONTROLLERS][CONFIG_DIMM_SLOTS_PER_CTLR]; 382 383 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) 384 fsl_ddr_get_spd(spd[i], i); 385 386 puts("SPD data of all dimms (zero vaule is omitted)...\n"); 387 puts("Byte (hex) "); 388 k = 1; 389 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) { 390 for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) 391 printf("Dimm%d ", k++); 392 } 393 puts("\n"); 394 for (k = 0; k < sizeof(generic_spd_eeprom_t); k++) { 395 m = 0; 396 printf("%3d (0x%02x) ", k, k); 397 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) { 398 for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) { 399 p_8 = (u8 *) &spd[i][j]; 400 if (p_8[k]) { 401 printf("0x%02x ", p_8[k]); 402 m++; 403 } else 404 puts(" "); 405 } 406 } 407 if (m) 408 puts("\n"); 409 else 410 puts("\r"); 411 } 412 413 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) { 414 switch (i) { 415 case 0: 416 ddr[i] = (void *)CONFIG_SYS_MPC85xx_DDR_ADDR; 417 break; 418 #ifdef CONFIG_SYS_MPC85xx_DDR2_ADDR 419 case 1: 420 ddr[i] = (void *)CONFIG_SYS_MPC85xx_DDR2_ADDR; 421 break; 422 #endif 423 default: 424 printf("%s unexpected controller number = %u\n", 425 __func__, i); 426 return; 427 } 428 } 429 printf("DDR registers dump for all controllers " 430 "(zero vaule is omitted)...\n"); 431 puts("Offset (hex) "); 432 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) 433 printf(" Base + 0x%04x", (u32)ddr[i] & 0xFFFF); 434 puts("\n"); 435 for (k = 0; k < sizeof(ccsr_ddr_t)/4; k++) { 436 m = 0; 437 printf("%6d (0x%04x)", k * 4, k * 4); 438 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) { 439 p_32 = (u32 *) ddr[i]; 440 if (p_32[k]) { 441 printf(" 0x%08x", p_32[k]); 442 m++; 443 } else 444 puts(" "); 445 } 446 if (m) 447 puts("\n"); 448 else 449 puts("\r"); 450 } 451 puts("\n"); 452 } 453 454 /* invalid the TLBs for DDR and setup new ones to cover p_addr */ 455 static int reset_tlb(phys_addr_t p_addr, u32 size, phys_addr_t *phys_offset) 456 { 457 u32 vstart = CONFIG_SYS_DDR_SDRAM_BASE; 458 unsigned long epn; 459 u32 tsize, valid, ptr; 460 int ddr_esel; 461 462 clear_ddr_tlbs_phys(p_addr, size>>20); 463 464 /* Setup new tlb to cover the physical address */ 465 setup_ddr_tlbs_phys(p_addr, size>>20); 466 467 ptr = vstart; 468 ddr_esel = find_tlb_idx((void *)ptr, 1); 469 if (ddr_esel != -1) { 470 read_tlbcam_entry(ddr_esel, &valid, &tsize, &epn, phys_offset); 471 } else { 472 printf("TLB error in function %s\n", __func__); 473 return -1; 474 } 475 476 return 0; 477 } 478 479 /* 480 * slide the testing window up to test another area 481 * for 32_bit system, the maximum testable memory is limited to 482 * CONFIG_MAX_MEM_MAPPED 483 */ 484 int arch_memory_test_advance(u32 *vstart, u32 *size, phys_addr_t *phys_offset) 485 { 486 phys_addr_t test_cap, p_addr; 487 phys_size_t p_size = min(gd->ram_size, CONFIG_MAX_MEM_MAPPED); 488 489 #if !defined(CONFIG_PHYS_64BIT) || \ 490 !defined(CONFIG_SYS_INIT_RAM_ADDR_PHYS) || \ 491 (CONFIG_SYS_INIT_RAM_ADDR_PHYS < 0x100000000ull) 492 test_cap = p_size; 493 #else 494 test_cap = gd->ram_size; 495 #endif 496 p_addr = (*vstart) + (*size) + (*phys_offset); 497 if (p_addr < test_cap - 1) { 498 p_size = min(test_cap - p_addr, CONFIG_MAX_MEM_MAPPED); 499 if (reset_tlb(p_addr, p_size, phys_offset) == -1) 500 return -1; 501 *vstart = CONFIG_SYS_DDR_SDRAM_BASE; 502 *size = (u32) p_size; 503 printf("Testing 0x%08llx - 0x%08llx\n", 504 (u64)(*vstart) + (*phys_offset), 505 (u64)(*vstart) + (*phys_offset) + (*size) - 1); 506 } else 507 return 1; 508 509 return 0; 510 } 511 512 /* initialization for testing area */ 513 int arch_memory_test_prepare(u32 *vstart, u32 *size, phys_addr_t *phys_offset) 514 { 515 phys_size_t p_size = min(gd->ram_size, CONFIG_MAX_MEM_MAPPED); 516 517 *vstart = CONFIG_SYS_DDR_SDRAM_BASE; 518 *size = (u32) p_size; /* CONFIG_MAX_MEM_MAPPED < 4G */ 519 *phys_offset = 0; 520 521 #if !defined(CONFIG_PHYS_64BIT) || \ 522 !defined(CONFIG_SYS_INIT_RAM_ADDR_PHYS) || \ 523 (CONFIG_SYS_INIT_RAM_ADDR_PHYS < 0x100000000ull) 524 if (gd->ram_size > CONFIG_MAX_MEM_MAPPED) { 525 puts("Cannot test more than "); 526 print_size(CONFIG_MAX_MEM_MAPPED, 527 " without proper 36BIT support.\n"); 528 } 529 #endif 530 printf("Testing 0x%08llx - 0x%08llx\n", 531 (u64)(*vstart) + (*phys_offset), 532 (u64)(*vstart) + (*phys_offset) + (*size) - 1); 533 534 return 0; 535 } 536 537 /* invalid TLBs for DDR and remap as normal after testing */ 538 int arch_memory_test_cleanup(u32 *vstart, u32 *size, phys_addr_t *phys_offset) 539 { 540 unsigned long epn; 541 u32 tsize, valid, ptr; 542 phys_addr_t rpn = 0; 543 int ddr_esel; 544 545 /* disable the TLBs for this testing */ 546 ptr = *vstart; 547 548 while (ptr < (*vstart) + (*size)) { 549 ddr_esel = find_tlb_idx((void *)ptr, 1); 550 if (ddr_esel != -1) { 551 read_tlbcam_entry(ddr_esel, &valid, &tsize, &epn, &rpn); 552 disable_tlb(ddr_esel); 553 } 554 ptr += TSIZE_TO_BYTES(tsize); 555 } 556 557 puts("Remap DDR "); 558 setup_ddr_tlbs(gd->ram_size>>20); 559 puts("\n"); 560 561 return 0; 562 } 563 564 void arch_memory_failure_handle(void) 565 { 566 dump_spd_ddr_reg(); 567 } 568 #endif 569