powerpc/mpc8xxx: Fix DDR initialization waiting for D_INIT

When ECC is enabled, DDR controller needs to initialize the data and ecc.
The wait time can be calcuated with total memory size, bus width,

powerpc/mpc8xxx: Fix DDR initialization waiting for D_INIT

When ECC is enabled, DDR controller needs to initialize the data and ecc.
The wait time can be calcuated with total memory size, bus width, bus speed
and interleaving mode. If it went wrong, it is bettert to timeout than
waiting for D_INIT to clear, where it probably hangs.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>

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powerpc/mpc8xxx: Fix DDR driver handling quad-rank DIMMs and address calculation

Fix handling quad-rank DIMMs in a system with two DIMM slots and first
slot supports both dual-rank DIMM and quad-ran

powerpc/mpc8xxx: Fix DDR driver handling quad-rank DIMMs and address calculation

Fix handling quad-rank DIMMs in a system with two DIMM slots and first
slot supports both dual-rank DIMM and quad-rank DIMM.

For systems with quad-rank DIMM and double dual-rank DIMMs, cs_config
registers need to be enabled to maintain proper ODT operation. The
inactive CS should have bnds registers cleared.

Fix the turnaround timing for systems with all chip-selects enabled. This
wasn't an issue before because DDR was running lower than 1600MT/s with
this interleaving mode.

Fix DDR address calculation. It wasn't an issue until we have multiple
controllers with each more than 4GB and interleaving is disabled.

It also fixes the message of DDR: 2 GiB (DDR3, 64-bit, CL=0.5, ECC off)
when debugging DDR and first DDR controller is disabled. With the fix,
the first enabled controller information will be displayed.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>

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powerpc/mpc8xxx: Update DDR registers

DDRC ver 4.7 adds DDR_SLOW bit in sdram_cfg_2 register. This bit needs to be
set for speed lower than 1250MT/s.

CDR1 and CDR2 are control driver registers. ODT

powerpc/mpc8xxx: Update DDR registers

DDRC ver 4.7 adds DDR_SLOW bit in sdram_cfg_2 register. This bit needs to be
set for speed lower than 1250MT/s.

CDR1 and CDR2 are control driver registers. ODT termination valueis for
IOs are defined. Starting from DDRC 4.7, the decoding of ODT for IOs is
000 -> Termsel off
001 -> 120 Ohm
010 -> 180 Ohm
011 -> 75 Ohm
100 -> 110 Ohm
101 -> 60 Ohm
110 -> 70 Ohm
111 -> 47 Ohm

Add two write leveling registers. Each QDS now has its own write leveling
start value. In case of zero value, the value of QDS0 will be used. These
values are board-specific and are set in board files.

Extend DDR register timing_cfg_1 to have 4 bits for each field.

DDR control driver registers and write leveling registers are added to
interactive debugging for easy access.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>

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powerpc/mpc85xx: Add B4860 and variant SoCs

Add support for Freescale B4860 and variant SoCs. Features of B4860 are
(incomplete list):

Six fully-programmable StarCore SC3900 FVP subsystems, divided

powerpc/mpc85xx: Add B4860 and variant SoCs

Add support for Freescale B4860 and variant SoCs. Features of B4860 are
(incomplete list):

Six fully-programmable StarCore SC3900 FVP subsystems, divided into three
clusters-each core runs up to 1.2 GHz, with an architecture highly
optimized for wireless base station applications
Four dual-thread e6500 Power Architecture processors organized in one
cluster-each core runs up to 1.8 GHz
Two DDR3/3L controllers for high-speed, industry-standard memory interface
each runs at up to 1866.67 MHz
MAPLE-B3 hardware acceleration-for forward error correction schemes
including Turbo or Viterbi decoding, Turbo encoding and rate matching,
MIMO MMSE equalization scheme, matrix operations, CRC insertion and
check, DFT/iDFT and FFT/iFFT calculations, PUSCH/PDSCH acceleration,
and UMTS chip rate acceleration
CoreNet fabric that fully supports coherency using MESI protocol between
the e6500 cores, SC3900 FVP cores, memories and external interfaces.
CoreNet fabric interconnect runs at 667 MHz and supports coherent and
non-coherent out of order transactions with prioritization and
bandwidth allocation amongst CoreNet endpoints.
Data Path Acceleration Architecture, which includes the following:
Frame Manager (FMan), which supports in-line packet parsing and general
classification to enable policing and QoS-based packet distribution
Queue Manager (QMan) and Buffer Manager (BMan), which allow offloading
of queue management, task management, load distribution, flow ordering,
buffer management, and allocation tasks from the cores
Security engine (SEC 5.3)-crypto-acceleration for protocols such as
IPsec, SSL, and 802.16
RapidIO manager (RMAN) - Support SRIO types 8, 9, 10, and 11 (inbound and
outbound). Supports types 5, 6 (outbound only)
Large internal cache memory with snooping and stashing capabilities for
bandwidth saving and high utilization of processor elements. The
9856-Kbyte internal memory space includes the following:
32 Kbyte L1 ICache per e6500/SC3900 core
32 Kbyte L1 DCache per e6500/SC3900 core
2048 Kbyte unified L2 cache for each SC3900 FVP cluster
2048 Kbyte unified L2 cache for the e6500 cluster
Two 512 Kbyte shared L3 CoreNet platform caches (CPC)
Sixteen 10-GHz SerDes lanes serving:
Two Serial RapidIO interfaces. Each supports up to 4 lanes and a total
of up to 8 lanes
Up to 8-lanes Common Public Radio Interface (CPRI) controller for glue-
less antenna connection
Two 10-Gbit Ethernet controllers (10GEC)
Six 1G/2.5-Gbit Ethernet controllers for network communications
PCI Express controller
Debug (Aurora)
Two OCeaN DMAs
Various system peripherals
182 32-bit timers

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>

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powerpc/mpc85xx: Add T4240 SoC

Add support for Freescale T4240 SoC. Feature of T4240 are
(incomplete list):

12 dual-threaded e6500 cores built on Power Architecture® technology
Arranged as cluste

powerpc/mpc85xx: Add T4240 SoC

Add support for Freescale T4240 SoC. Feature of T4240 are
(incomplete list):

12 dual-threaded e6500 cores built on Power Architecture® technology
Arranged as clusters of four cores sharing a 2 MB L2 cache.
Up to 1.8 GHz at 1.0 V with 64-bit ISA support (Power Architecture
v2.06-compliant)
Three levels of instruction: user, supervisor, and hypervisor
1.5 MB CoreNet Platform Cache (CPC)
Hierarchical interconnect fabric
CoreNet fabric supporting coherent and non-coherent transactions with
prioritization and bandwidth allocation amongst CoreNet end-points
1.6 Tbps coherent read bandwidth
Queue Manager (QMan) fabric supporting packet-level queue management and
quality of service scheduling
Three 64-bit DDR3/3L SDRAM memory controllers with ECC and interleaving
support
Memory prefetch engine (PMan)
Data Path Acceleration Architecture (DPAA) incorporating acceleration for
the following functions:
Packet parsing, classification, and distribution (Frame Manager 1.1)
Queue management for scheduling, packet sequencing, and congestion
management (Queue Manager 1.1)
Hardware buffer management for buffer allocation and de-allocation
(BMan 1.1)
Cryptography acceleration (SEC 5.0) at up to 40 Gbps
RegEx Pattern Matching Acceleration (PME 2.1) at up to 10 Gbps
Decompression/Compression Acceleration (DCE 1.0) at up to 20 Gbps
DPAA chip-to-chip interconnect via RapidIO Message Manager (RMAN 1.0)
32 SerDes lanes at up to 10.3125 GHz
Ethernet interfaces
Up to four 10 Gbps Ethernet MACs
Up to sixteen 1 Gbps Ethernet MACs
Maximum configuration of 4 x 10 GE + 8 x 1 GE
High-speed peripheral interfaces
Four PCI Express 2.0/3.0 controllers
Two Serial RapidIO 2.0 controllers/ports running at up to 5 GHz with
Type 11 messaging and Type 9 data streaming support
Interlaken look-aside interface for serial TCAM connection
Additional peripheral interfaces
Two serial ATA (SATA 2.0) controllers
Two high-speed USB 2.0 controllers with integrated PHY
Enhanced secure digital host controller (SD/MMC/eMMC)
Enhanced serial peripheral interface (eSPI)
Four I2C controllers
Four 2-pin or two 4-pin UARTs
Integrated Flash controller supporting NAND and NOR flash
Two eight-channel DMA engines
Support for hardware virtualization and partitioning enforcement
QorIQ Platform's Trust Architecture 1.1

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Signed-off-by: Andy Fleming <afleming@freescale.com>
Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>

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powerpc/corenet2: fix mismatch DDR sync bit from RCW

Corenet 2nd generation Chassis doesn't have ddr_sync bit in RCW. Only
async mode is supported.

Signed-off-by: York Sun <yorksun@freescale.com>
S

powerpc/corenet2: fix mismatch DDR sync bit from RCW

Corenet 2nd generation Chassis doesn't have ddr_sync bit in RCW. Only
async mode is supported.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>

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powerpc/corenet2: Add SerDes for corenet2

Create new files to handle 2nd generation Chassis as the registers are
organized differently.

- Add SerDes protocol parsing and detection
- Add support o

powerpc/corenet2: Add SerDes for corenet2

Create new files to handle 2nd generation Chassis as the registers are
organized differently.

- Add SerDes protocol parsing and detection
- Add support of 4 SerDes
- Add CPRI protocol in fsl_serdes.h
The Common Public Radio Interface (CPRI) is publicly available
specification that standardizes the protocol interface between the
radio equipment control (REC) and the radio equipment (RE) in wireless
basestations. This allows interoperability of equipment from different
vendors,and preserves the software investment made by wireless service
providers.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>

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powerpc/mpc85xx: Fix core cluster PLL calculation for Chassis generation 2

Corenet based SoCs have different core clocks starting from Chassis
generation 2. Cores are organized into clusters. Each c

powerpc/mpc85xx: Fix core cluster PLL calculation for Chassis generation 2

Corenet based SoCs have different core clocks starting from Chassis
generation 2. Cores are organized into clusters. Each cluster has up to
4 cores sharing same clock, which can be chosen from one of three PLLs in
the cluster group with one of the devisors /1, /2 or /4. Two clusters are
put together as a cluster group. These two clusters share the PLLs but may
have different divisor. For example, core 0~3 are in cluster 1. Core 4~7
are in cluster 2. Core 8~11 are in cluster 3 and so on. Cluster 1 and 2
are cluster group A. Cluster 3 and 4 are in cluster group B. Cluster group
A has PLL1, PLL2, PLL3. Cluster group B has PLL4, PLL5. Core 0~3 may have
PLL1/2, core 4~7 may have PLL2/2. Core 8~11 may have PLL4/1.

PME and FMan blocks can take different PLLs, configured by RCW.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>

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powerpc/mpc85xx: check number of cores

Panic if the number of cores is more than CONFIG_MAX_CPUS because it will
surely overflow gd structure.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed

powerpc/mpc85xx: check number of cores

Panic if the number of cores is more than CONFIG_MAX_CPUS because it will
surely overflow gd structure.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>

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powerpc/mpc85xx: change RCW MEM_PLL_PLAT for Chassis generation 2

Chassis generation 2 has different mask and shift. Use macro instead of
magic numbers.

Signed-off-by: York Sun <yorksun@freescale.c

powerpc/mpc85xx: change RCW MEM_PLL_PLAT for Chassis generation 2

Chassis generation 2 has different mask and shift. Use macro instead of
magic numbers.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>

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powerpc/mpc85xx: Enable L2 at the beginning of U-boot for E6500

Using E6500 L1 cache as initram requires L2 cache enabled.
Add l2-cache cluster enabling.

Setup stash id for L1 cache as (coreID) * 2

powerpc/mpc85xx: Enable L2 at the beginning of U-boot for E6500

Using E6500 L1 cache as initram requires L2 cache enabled.
Add l2-cache cluster enabling.

Setup stash id for L1 cache as (coreID) * 2 + 32 + 0
Setup stash id for L2 cache as (cluster) * 2 + 32 + 1
Stash id for L2 is only set for Chassis 2.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Signed-off-by: Andy Fleming <afleming@freescale.com>

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powerpc/mpc85xx: Introduce new macros to add and delete TLB entries

These assembly macros simplify codes to add and delete temporary TLB entries.

Signed-off-by: York Sun <yorksun@freescale.com>
Sig

powerpc/mpc85xx: Introduce new macros to add and delete TLB entries

These assembly macros simplify codes to add and delete temporary TLB entries.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>

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powerpc/85xx: Add determining and report IFC frequency

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Signed-off-by: Andy Fleming <afleming@freescale.com>

powerpc/85xx: Add P5040 processor support

Add support for the Freescale P5040 SOC, which is similar to the P5020.
Features of the P5040 are:

Four P5040 single-threaded e5500 cores built
Up to 2

powerpc/85xx: Add P5040 processor support

Add support for the Freescale P5040 SOC, which is similar to the P5020.
Features of the P5040 are:

Four P5040 single-threaded e5500 cores built
Up to 2.4 GHz with 64-bit ISA support
Three levels of instruction: user, supervisor, hypervisor
CoreNet platform cache (CPC)
2.0 MB configures as dual 1 MB blocks hierarchical interconnect fabric
Two 64-bit DDR3/3L SDRAM memory controllers with ECC and interleaving
support Up to 1600MT/s
Memory pre-fetch engine
DPAA incorporating acceleration for the following functions
Packet parsing, classification, and distribution (FMAN)
Queue management for scheduling, packet sequencing and
congestion management (QMAN)
Hardware buffer management for buffer allocation and
de-allocation (BMAN)
Cryptography acceleration (SEC 5.2) at up to 40 Gbps SerDes
20 lanes at up to 5 Gbps
Supports SGMII, XAUI, PCIe rev1.1/2.0, SATA Ethernet interfaces
Two 10 Gbps Ethernet MACs
Ten 1 Gbps Ethernet MACs
High-speed peripheral interfaces
Two PCI Express 2.0/3.0 controllers
Additional peripheral interfaces
Two serial ATA (SATA 2.0) controllers
Two high-speed USB 2.0 controllers with integrated PHY
Enhanced secure digital host controller (SD/MMC/eMMC)
Enhanced serial peripheral interface (eSPI)
Two I2C controllers
Four UARTs
Integrated flash controller supporting NAND and NOR flash
DMA
Dual four channel
Support for hardware virtualization and partitioning enforcement
Extra privileged level for hypervisor support
QorIQ Trust Architecture 1.1
Secure boot, secure debug, tamper detection, volatile key storage

Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>

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powerpc/p5040ds: add per pci endpoint liodn offset list

Add a new device tree property named "fsl,liodn-offset-list"
holding a list of per pci endpoint permitted liodn offsets.
This property is usef

powerpc/p5040ds: add per pci endpoint liodn offset list

Add a new device tree property named "fsl,liodn-offset-list"
holding a list of per pci endpoint permitted liodn offsets.
This property is useful in virtualization scenarios
that implement per pci endpoint partitioning.
The final liodn of a partitioned pci endpoint is
calculated by the hardware, by adding these offsets
to pci controller's base liodn, stored in the
"fsl,liodn" property of its node.
The liodn offsets are interleaved to get better cache
utilization. As an example, given 3 pci controllers,
the following liodns are generated for the pci endpoints:
pci0: 193 256 259 262 265 268 271 274 277
pci1: 194 257 260 263 266 269 272 275 278
pci2: 195 258 261 264 267 270 273 276 279

Signed-off-by: Laurentiu Tudor <Laurentiu.Tudor@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>

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powerpc/85xx: define SRIO LIODN functions only if SRIO is defined

The P5040 does not have SRIO support, so there are no SRIO LIODNs.
Therefore, the functions that set the SRIO LIODNs should not be c

powerpc/85xx: define SRIO LIODN functions only if SRIO is defined

The P5040 does not have SRIO support, so there are no SRIO LIODNs.
Therefore, the functions that set the SRIO LIODNs should not be compiled.

Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>

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powerpc/mpc85xx: fix Unicode characters in release.S

Commit 709389b6 unintentionally used the Unicode version of the
apostrophy. Replace it with the normal ASCII version.

Signed-off-by: Timur Tabi

powerpc/mpc85xx: fix Unicode characters in release.S

Commit 709389b6 unintentionally used the Unicode version of the
apostrophy. Replace it with the normal ASCII version.

Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>

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powerpc/srio: Workaround for srio erratrm a004034

Erratum: A-004034
Affects: SRIO

Description: During port initialization, the SRIO port performs
lane synchronization (detecting valid symbols on a

powerpc/srio: Workaround for srio erratrm a004034

Erratum: A-004034
Affects: SRIO

Description: During port initialization, the SRIO port performs
lane synchronization (detecting valid symbols on a lane) and
lane alignment (coordinating multiple lanes to receive valid data
across lanes). Internal errors in lane synchronization and lane
alignment may cause failure to achieve link initialization at
the configured port width.

An SRIO port configured as a 4x port may see one of these scenarios:

1. One or more lanes fails to achieve lane synchronization.
Depending on which lanes fail, this may result in downtraining
from 4x to 1x on lane 0, 4x to 1x on lane R (redundant lane).

2. The link may fail to achieve lane alignment as a 4x, even
though all 4 lanes achieve lane synchronization, and downtrain
to a 1x. An SRIO port configured as a 1x port may fail to complete
port initialization (PnESCSR[PU] never deasserts) because of
scenario 1.

Impact: SRIO port may downtrain to 1x, or may fail to complete
link initialization. Once a port completes link initialization
successfully, it will operate normally.

Signed-off-by: Liu Gang <Gang.Liu@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>

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powerpc/mpc8xxx: Fix USB device-tree fixup

Fix usb device-tree fixup:
- wrong modification of dr_mode and phy_type when
"usb1" is not mentioned inside hwconfig string;
now allows hwconfig st

powerpc/mpc8xxx: Fix USB device-tree fixup

Fix usb device-tree fixup:
- wrong modification of dr_mode and phy_type when
"usb1" is not mentioned inside hwconfig string;
now allows hwconfig strings like:
"usb2:dr_mode=host,phy_type=ulpi"
- add warning message for using usb_dr_mode
and usb_phy_type env variables (if either is used)

Signed-off-by: Ramneek Mehresh <ramneek.mehresh@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>

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common: Discard the __u_boot_cmd section

The command declaration now uses the new LG-array method to generate
list of commands. Thus the __u_boot_cmd section is now superseded and
redundant and ther

common: Discard the __u_boot_cmd section

The command declaration now uses the new LG-array method to generate
list of commands. Thus the __u_boot_cmd section is now superseded and
redundant and therefore can be removed. Also, remove externed symbols
associated with this section from include/command.h .

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Joe Hershberger <joe.hershberger@gmail.com>
Cc: Mike Frysinger <vapier@gentoo.org>

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common: Add .u_boot_list into all linker files

Add section for the linker-generated lists into all possible linker
files, so that everyone can easily use these lists. This is mostly
a mechanical adj

common: Add .u_boot_list into all linker files

Add section for the linker-generated lists into all possible linker
files, so that everyone can easily use these lists. This is mostly
a mechanical adjustment.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Joe Hershberger <joe.hershberger@gmail.com>
Cc: Mike Frysinger <vapier@gentoo.org>

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P4080/esdhc: make the P4080 ESDHC13 errata workaround conditional

P4080 Rev3.0 fixes ESDHC13 errata, so update the code to make the
workaround conditional.
In formal release document, the errata num

P4080/esdhc: make the P4080 ESDHC13 errata workaround conditional

P4080 Rev3.0 fixes ESDHC13 errata, so update the code to make the
workaround conditional.
In formal release document, the errata number should be ESDHC13 instead
of ESDHC136.

Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>

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powerpc mpc85xx: Only clear TSR:WIS in watchdog_reset.

We should only write TSR_WIS to the SPRN_TSR register in
reset_85xx_watchdog.

The old code would cause the timer interrupt to be acknowledged

powerpc mpc85xx: Only clear TSR:WIS in watchdog_reset.

We should only write TSR_WIS to the SPRN_TSR register in
reset_85xx_watchdog.

The old code would cause the timer interrupt to be acknowledged when the
watchdog was reset, and we would then get no more timer interrupts.
This bug would affect all mpc85xx boards that have the watchdog enabled.

Signed-off-by: Mark Marshall <Mark.Marshall@omicron.at>
Signed-off-by: Andy Fleming <afleming@freescale.com>

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serial: Use default_serial_puts() in drivers

Replace the in-place ad-hoc implementation of serial_puts() within
the drivers with default_serial_puts() call. This cuts down on the
code duplication qu

serial: Use default_serial_puts() in drivers

Replace the in-place ad-hoc implementation of serial_puts() within
the drivers with default_serial_puts() call. This cuts down on the
code duplication quite a bit.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Marek Vasut <marek.vasut@gmail.com>
Cc: Tom Rini <trini@ti.com>

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mpc82xx: Remove BMW board port

As the board seems to be unmaintained for some time, lets remove
the support in mainline completely.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Marek Vasut <marek.v

mpc82xx: Remove BMW board port

As the board seems to be unmaintained for some time, lets remove
the support in mainline completely.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Marek Vasut <marek.vasut@gmail.com>
Cc: James F. Dougherty <jfd@broadcom.com>
Cc: Wolfgang Denk <wd@denx.de>
Acked-by: Marek Vasut <marex@denx.de>

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