1 /* 2 * Copyright 2007-2011 Freescale Semiconductor, Inc. 3 * 4 * (C) Copyright 2000 5 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 6 * 7 * See file CREDITS for list of people who contributed to this 8 * project. 9 * 10 * This program is free software; you can redistribute it and/or 11 * modify it under the terms of the GNU General Public License as 12 * published by the Free Software Foundation; either version 2 of 13 * the License, or (at your option) any later version. 14 * 15 * This program is distributed in the hope that it will be useful, 16 * but WITHOUT ANY WARRANTY; without even the implied warranty of 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18 * GNU General Public License for more details. 19 * 20 * You should have received a copy of the GNU General Public License 21 * along with this program; if not, write to the Free Software 22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 23 * MA 02111-1307 USA 24 */ 25 26 #include <common.h> 27 #include <libfdt.h> 28 #include <fdt_support.h> 29 #include <asm/processor.h> 30 #include <linux/ctype.h> 31 #include <asm/io.h> 32 #include <asm/fsl_portals.h> 33 #ifdef CONFIG_FSL_ESDHC 34 #include <fsl_esdhc.h> 35 #endif 36 #include "../../../../drivers/qe/qe.h" /* For struct qe_firmware */ 37 38 DECLARE_GLOBAL_DATA_PTR; 39 40 extern void ft_qe_setup(void *blob); 41 extern void ft_fixup_num_cores(void *blob); 42 extern void ft_srio_setup(void *blob); 43 44 #ifdef CONFIG_MP 45 #include "mp.h" 46 47 void ft_fixup_cpu(void *blob, u64 memory_limit) 48 { 49 int off; 50 ulong spin_tbl_addr = get_spin_phys_addr(); 51 u32 bootpg = determine_mp_bootpg(); 52 u32 id = get_my_id(); 53 const char *enable_method; 54 55 off = fdt_node_offset_by_prop_value(blob, -1, "device_type", "cpu", 4); 56 while (off != -FDT_ERR_NOTFOUND) { 57 u32 *reg = (u32 *)fdt_getprop(blob, off, "reg", 0); 58 59 if (reg) { 60 u32 phys_cpu_id = thread_to_core(*reg); 61 u64 val = phys_cpu_id * SIZE_BOOT_ENTRY + spin_tbl_addr; 62 val = cpu_to_fdt64(val); 63 if (*reg == id) { 64 fdt_setprop_string(blob, off, "status", 65 "okay"); 66 } else { 67 fdt_setprop_string(blob, off, "status", 68 "disabled"); 69 } 70 71 if (hold_cores_in_reset(0)) { 72 #ifdef CONFIG_FSL_CORENET 73 /* Cores held in reset, use BRR to release */ 74 enable_method = "fsl,brr-holdoff"; 75 #else 76 /* Cores held in reset, use EEBPCR to release */ 77 enable_method = "fsl,eebpcr-holdoff"; 78 #endif 79 } else { 80 /* Cores out of reset and in a spin-loop */ 81 enable_method = "spin-table"; 82 83 fdt_setprop(blob, off, "cpu-release-addr", 84 &val, sizeof(val)); 85 } 86 87 fdt_setprop_string(blob, off, "enable-method", 88 enable_method); 89 } else { 90 printf ("cpu NULL\n"); 91 } 92 off = fdt_node_offset_by_prop_value(blob, off, 93 "device_type", "cpu", 4); 94 } 95 96 /* Reserve the boot page so OSes dont use it */ 97 if ((u64)bootpg < memory_limit) { 98 off = fdt_add_mem_rsv(blob, bootpg, (u64)4096); 99 if (off < 0) 100 printf("%s: %s\n", __FUNCTION__, fdt_strerror(off)); 101 } 102 } 103 #endif 104 105 #ifdef CONFIG_SYS_FSL_CPC 106 static inline void ft_fixup_l3cache(void *blob, int off) 107 { 108 u32 line_size, num_ways, size, num_sets; 109 cpc_corenet_t *cpc = (void *)CONFIG_SYS_FSL_CPC_ADDR; 110 u32 cfg0 = in_be32(&cpc->cpccfg0); 111 112 size = CPC_CFG0_SZ_K(cfg0) * 1024 * CONFIG_SYS_NUM_CPC; 113 num_ways = CPC_CFG0_NUM_WAYS(cfg0); 114 line_size = CPC_CFG0_LINE_SZ(cfg0); 115 num_sets = size / (line_size * num_ways); 116 117 fdt_setprop(blob, off, "cache-unified", NULL, 0); 118 fdt_setprop_cell(blob, off, "cache-block-size", line_size); 119 fdt_setprop_cell(blob, off, "cache-size", size); 120 fdt_setprop_cell(blob, off, "cache-sets", num_sets); 121 fdt_setprop_cell(blob, off, "cache-level", 3); 122 #ifdef CONFIG_SYS_CACHE_STASHING 123 fdt_setprop_cell(blob, off, "cache-stash-id", 1); 124 #endif 125 } 126 #else 127 #define ft_fixup_l3cache(x, y) 128 #endif 129 130 #if defined(CONFIG_L2_CACHE) 131 /* return size in kilobytes */ 132 static inline u32 l2cache_size(void) 133 { 134 volatile ccsr_l2cache_t *l2cache = (void *)CONFIG_SYS_MPC85xx_L2_ADDR; 135 volatile u32 l2siz_field = (l2cache->l2ctl >> 28) & 0x3; 136 u32 ver = SVR_SOC_VER(get_svr()); 137 138 switch (l2siz_field) { 139 case 0x0: 140 break; 141 case 0x1: 142 if (ver == SVR_8540 || ver == SVR_8560 || 143 ver == SVR_8541 || ver == SVR_8555) 144 return 128; 145 else 146 return 256; 147 break; 148 case 0x2: 149 if (ver == SVR_8540 || ver == SVR_8560 || 150 ver == SVR_8541 || ver == SVR_8555) 151 return 256; 152 else 153 return 512; 154 break; 155 case 0x3: 156 return 1024; 157 break; 158 } 159 160 return 0; 161 } 162 163 static inline void ft_fixup_l2cache(void *blob) 164 { 165 int len, off; 166 u32 *ph; 167 struct cpu_type *cpu = identify_cpu(SVR_SOC_VER(get_svr())); 168 169 const u32 line_size = 32; 170 const u32 num_ways = 8; 171 const u32 size = l2cache_size() * 1024; 172 const u32 num_sets = size / (line_size * num_ways); 173 174 off = fdt_node_offset_by_prop_value(blob, -1, "device_type", "cpu", 4); 175 if (off < 0) { 176 debug("no cpu node fount\n"); 177 return; 178 } 179 180 ph = (u32 *)fdt_getprop(blob, off, "next-level-cache", 0); 181 182 if (ph == NULL) { 183 debug("no next-level-cache property\n"); 184 return ; 185 } 186 187 off = fdt_node_offset_by_phandle(blob, *ph); 188 if (off < 0) { 189 printf("%s: %s\n", __func__, fdt_strerror(off)); 190 return ; 191 } 192 193 if (cpu) { 194 char buf[40]; 195 196 if (isdigit(cpu->name[0])) { 197 /* MPCxxxx, where xxxx == 4-digit number */ 198 len = sprintf(buf, "fsl,mpc%s-l2-cache-controller", 199 cpu->name) + 1; 200 } else { 201 /* Pxxxx or Txxxx, where xxxx == 4-digit number */ 202 len = sprintf(buf, "fsl,%c%s-l2-cache-controller", 203 tolower(cpu->name[0]), cpu->name + 1) + 1; 204 } 205 206 /* 207 * append "cache" after the NULL character that the previous 208 * sprintf wrote. This is how a device tree stores multiple 209 * strings in a property. 210 */ 211 len += sprintf(buf + len, "cache") + 1; 212 213 fdt_setprop(blob, off, "compatible", buf, len); 214 } 215 fdt_setprop(blob, off, "cache-unified", NULL, 0); 216 fdt_setprop_cell(blob, off, "cache-block-size", line_size); 217 fdt_setprop_cell(blob, off, "cache-size", size); 218 fdt_setprop_cell(blob, off, "cache-sets", num_sets); 219 fdt_setprop_cell(blob, off, "cache-level", 2); 220 221 /* we dont bother w/L3 since no platform of this type has one */ 222 } 223 #elif defined(CONFIG_BACKSIDE_L2_CACHE) || \ 224 defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2) 225 static inline void ft_fixup_l2cache(void *blob) 226 { 227 int off, l2_off, l3_off = -1; 228 u32 *ph; 229 #ifdef CONFIG_BACKSIDE_L2_CACHE 230 u32 l2cfg0 = mfspr(SPRN_L2CFG0); 231 #else 232 struct ccsr_cluster_l2 *l2cache = 233 (struct ccsr_cluster_l2 __iomem *)(CONFIG_SYS_FSL_CLUSTER_1_L2); 234 u32 l2cfg0 = in_be32(&l2cache->l2cfg0); 235 #endif 236 u32 size, line_size, num_ways, num_sets; 237 int has_l2 = 1; 238 239 /* P2040/P2040E has no L2, so dont set any L2 props */ 240 if (SVR_SOC_VER(get_svr()) == SVR_P2040) 241 has_l2 = 0; 242 243 size = (l2cfg0 & 0x3fff) * 64 * 1024; 244 num_ways = ((l2cfg0 >> 14) & 0x1f) + 1; 245 line_size = (((l2cfg0 >> 23) & 0x3) + 1) * 32; 246 num_sets = size / (line_size * num_ways); 247 248 off = fdt_node_offset_by_prop_value(blob, -1, "device_type", "cpu", 4); 249 250 while (off != -FDT_ERR_NOTFOUND) { 251 ph = (u32 *)fdt_getprop(blob, off, "next-level-cache", 0); 252 253 if (ph == NULL) { 254 debug("no next-level-cache property\n"); 255 goto next; 256 } 257 258 l2_off = fdt_node_offset_by_phandle(blob, *ph); 259 if (l2_off < 0) { 260 printf("%s: %s\n", __func__, fdt_strerror(off)); 261 goto next; 262 } 263 264 if (has_l2) { 265 #ifdef CONFIG_SYS_CACHE_STASHING 266 u32 *reg = (u32 *)fdt_getprop(blob, off, "reg", 0); 267 #ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2 268 /* Only initialize every eighth thread */ 269 if (reg && !((*reg) % 8)) 270 #else 271 if (reg) 272 #endif 273 fdt_setprop_cell(blob, l2_off, "cache-stash-id", 274 (*reg * 2) + 32 + 1); 275 #endif 276 277 fdt_setprop(blob, l2_off, "cache-unified", NULL, 0); 278 fdt_setprop_cell(blob, l2_off, "cache-block-size", 279 line_size); 280 fdt_setprop_cell(blob, l2_off, "cache-size", size); 281 fdt_setprop_cell(blob, l2_off, "cache-sets", num_sets); 282 fdt_setprop_cell(blob, l2_off, "cache-level", 2); 283 fdt_setprop(blob, l2_off, "compatible", "cache", 6); 284 } 285 286 if (l3_off < 0) { 287 ph = (u32 *)fdt_getprop(blob, l2_off, "next-level-cache", 0); 288 289 if (ph == NULL) { 290 debug("no next-level-cache property\n"); 291 goto next; 292 } 293 l3_off = *ph; 294 } 295 next: 296 off = fdt_node_offset_by_prop_value(blob, off, 297 "device_type", "cpu", 4); 298 } 299 if (l3_off > 0) { 300 l3_off = fdt_node_offset_by_phandle(blob, l3_off); 301 if (l3_off < 0) { 302 printf("%s: %s\n", __func__, fdt_strerror(off)); 303 return ; 304 } 305 ft_fixup_l3cache(blob, l3_off); 306 } 307 } 308 #else 309 #define ft_fixup_l2cache(x) 310 #endif 311 312 static inline void ft_fixup_cache(void *blob) 313 { 314 int off; 315 316 off = fdt_node_offset_by_prop_value(blob, -1, "device_type", "cpu", 4); 317 318 while (off != -FDT_ERR_NOTFOUND) { 319 u32 l1cfg0 = mfspr(SPRN_L1CFG0); 320 u32 l1cfg1 = mfspr(SPRN_L1CFG1); 321 u32 isize, iline_size, inum_sets, inum_ways; 322 u32 dsize, dline_size, dnum_sets, dnum_ways; 323 324 /* d-side config */ 325 dsize = (l1cfg0 & 0x7ff) * 1024; 326 dnum_ways = ((l1cfg0 >> 11) & 0xff) + 1; 327 dline_size = (((l1cfg0 >> 23) & 0x3) + 1) * 32; 328 dnum_sets = dsize / (dline_size * dnum_ways); 329 330 fdt_setprop_cell(blob, off, "d-cache-block-size", dline_size); 331 fdt_setprop_cell(blob, off, "d-cache-size", dsize); 332 fdt_setprop_cell(blob, off, "d-cache-sets", dnum_sets); 333 334 #ifdef CONFIG_SYS_CACHE_STASHING 335 { 336 u32 *reg = (u32 *)fdt_getprop(blob, off, "reg", 0); 337 if (reg) 338 fdt_setprop_cell(blob, off, "cache-stash-id", 339 (*reg * 2) + 32 + 0); 340 } 341 #endif 342 343 /* i-side config */ 344 isize = (l1cfg1 & 0x7ff) * 1024; 345 inum_ways = ((l1cfg1 >> 11) & 0xff) + 1; 346 iline_size = (((l1cfg1 >> 23) & 0x3) + 1) * 32; 347 inum_sets = isize / (iline_size * inum_ways); 348 349 fdt_setprop_cell(blob, off, "i-cache-block-size", iline_size); 350 fdt_setprop_cell(blob, off, "i-cache-size", isize); 351 fdt_setprop_cell(blob, off, "i-cache-sets", inum_sets); 352 353 off = fdt_node_offset_by_prop_value(blob, off, 354 "device_type", "cpu", 4); 355 } 356 357 ft_fixup_l2cache(blob); 358 } 359 360 361 void fdt_add_enet_stashing(void *fdt) 362 { 363 do_fixup_by_compat(fdt, "gianfar", "bd-stash", NULL, 0, 1); 364 365 do_fixup_by_compat_u32(fdt, "gianfar", "rx-stash-len", 96, 1); 366 367 do_fixup_by_compat_u32(fdt, "gianfar", "rx-stash-idx", 0, 1); 368 do_fixup_by_compat(fdt, "fsl,etsec2", "bd-stash", NULL, 0, 1); 369 do_fixup_by_compat_u32(fdt, "fsl,etsec2", "rx-stash-len", 96, 1); 370 do_fixup_by_compat_u32(fdt, "fsl,etsec2", "rx-stash-idx", 0, 1); 371 } 372 373 #if defined(CONFIG_SYS_DPAA_FMAN) || defined(CONFIG_SYS_DPAA_PME) 374 #ifdef CONFIG_SYS_DPAA_FMAN 375 static void ft_fixup_clks(void *blob, const char *compat, u32 offset, 376 unsigned long freq) 377 { 378 phys_addr_t phys = offset + CONFIG_SYS_CCSRBAR_PHYS; 379 int off = fdt_node_offset_by_compat_reg(blob, compat, phys); 380 381 if (off >= 0) { 382 off = fdt_setprop_cell(blob, off, "clock-frequency", freq); 383 if (off > 0) 384 printf("WARNING enable to set clock-frequency " 385 "for %s: %s\n", compat, fdt_strerror(off)); 386 } 387 } 388 #endif 389 390 static void ft_fixup_dpaa_clks(void *blob) 391 { 392 sys_info_t sysinfo; 393 394 get_sys_info(&sysinfo); 395 #ifdef CONFIG_SYS_DPAA_FMAN 396 ft_fixup_clks(blob, "fsl,fman", CONFIG_SYS_FSL_FM1_OFFSET, 397 sysinfo.freqFMan[0]); 398 399 #if (CONFIG_SYS_NUM_FMAN == 2) 400 ft_fixup_clks(blob, "fsl,fman", CONFIG_SYS_FSL_FM2_OFFSET, 401 sysinfo.freqFMan[1]); 402 #endif 403 #endif 404 405 #ifdef CONFIG_SYS_DPAA_PME 406 do_fixup_by_compat_u32(blob, "fsl,pme", 407 "clock-frequency", sysinfo.freqPME, 1); 408 #endif 409 } 410 #else 411 #define ft_fixup_dpaa_clks(x) 412 #endif 413 414 #ifdef CONFIG_QE 415 static void ft_fixup_qe_snum(void *blob) 416 { 417 unsigned int svr; 418 419 svr = mfspr(SPRN_SVR); 420 if (SVR_SOC_VER(svr) == SVR_8569) { 421 if(IS_SVR_REV(svr, 1, 0)) 422 do_fixup_by_compat_u32(blob, "fsl,qe", 423 "fsl,qe-num-snums", 46, 1); 424 else 425 do_fixup_by_compat_u32(blob, "fsl,qe", 426 "fsl,qe-num-snums", 76, 1); 427 } 428 } 429 #endif 430 431 /** 432 * fdt_fixup_fman_firmware -- insert the Fman firmware into the device tree 433 * 434 * The binding for an Fman firmware node is documented in 435 * Documentation/powerpc/dts-bindings/fsl/dpaa/fman.txt. This node contains 436 * the actual Fman firmware binary data. The operating system is expected to 437 * be able to parse the binary data to determine any attributes it needs. 438 */ 439 #ifdef CONFIG_SYS_DPAA_FMAN 440 void fdt_fixup_fman_firmware(void *blob) 441 { 442 int rc, fmnode, fwnode = -1; 443 uint32_t phandle; 444 struct qe_firmware *fmanfw; 445 const struct qe_header *hdr; 446 unsigned int length; 447 uint32_t crc; 448 const char *p; 449 450 /* The first Fman we find will contain the actual firmware. */ 451 fmnode = fdt_node_offset_by_compatible(blob, -1, "fsl,fman"); 452 if (fmnode < 0) 453 /* Exit silently if there are no Fman devices */ 454 return; 455 456 /* If we already have a firmware node, then also exit silently. */ 457 if (fdt_node_offset_by_compatible(blob, -1, "fsl,fman-firmware") > 0) 458 return; 459 460 /* If the environment variable is not set, then exit silently */ 461 p = getenv("fman_ucode"); 462 if (!p) 463 return; 464 465 fmanfw = (struct qe_firmware *) simple_strtoul(p, NULL, 0); 466 if (!fmanfw) 467 return; 468 469 hdr = &fmanfw->header; 470 length = be32_to_cpu(hdr->length); 471 472 /* Verify the firmware. */ 473 if ((hdr->magic[0] != 'Q') || (hdr->magic[1] != 'E') || 474 (hdr->magic[2] != 'F')) { 475 printf("Data at %p is not an Fman firmware\n", fmanfw); 476 return; 477 } 478 479 if (length > CONFIG_SYS_QE_FMAN_FW_LENGTH) { 480 printf("Fman firmware at %p is too large (size=%u)\n", 481 fmanfw, length); 482 return; 483 } 484 485 length -= sizeof(u32); /* Subtract the size of the CRC */ 486 crc = be32_to_cpu(*(u32 *)((void *)fmanfw + length)); 487 if (crc != crc32_no_comp(0, (void *)fmanfw, length)) { 488 printf("Fman firmware at %p has invalid CRC\n", fmanfw); 489 return; 490 } 491 492 /* Increase the size of the fdt to make room for the node. */ 493 rc = fdt_increase_size(blob, fmanfw->header.length); 494 if (rc < 0) { 495 printf("Unable to make room for Fman firmware: %s\n", 496 fdt_strerror(rc)); 497 return; 498 } 499 500 /* Create the firmware node. */ 501 fwnode = fdt_add_subnode(blob, fmnode, "fman-firmware"); 502 if (fwnode < 0) { 503 char s[64]; 504 fdt_get_path(blob, fmnode, s, sizeof(s)); 505 printf("Could not add firmware node to %s: %s\n", s, 506 fdt_strerror(fwnode)); 507 return; 508 } 509 rc = fdt_setprop_string(blob, fwnode, "compatible", "fsl,fman-firmware"); 510 if (rc < 0) { 511 char s[64]; 512 fdt_get_path(blob, fwnode, s, sizeof(s)); 513 printf("Could not add compatible property to node %s: %s\n", s, 514 fdt_strerror(rc)); 515 return; 516 } 517 phandle = fdt_create_phandle(blob, fwnode); 518 if (!phandle) { 519 char s[64]; 520 fdt_get_path(blob, fwnode, s, sizeof(s)); 521 printf("Could not add phandle property to node %s: %s\n", s, 522 fdt_strerror(rc)); 523 return; 524 } 525 rc = fdt_setprop(blob, fwnode, "fsl,firmware", fmanfw, fmanfw->header.length); 526 if (rc < 0) { 527 char s[64]; 528 fdt_get_path(blob, fwnode, s, sizeof(s)); 529 printf("Could not add firmware property to node %s: %s\n", s, 530 fdt_strerror(rc)); 531 return; 532 } 533 534 /* Find all other Fman nodes and point them to the firmware node. */ 535 while ((fmnode = fdt_node_offset_by_compatible(blob, fmnode, "fsl,fman")) > 0) { 536 rc = fdt_setprop_cell(blob, fmnode, "fsl,firmware-phandle", phandle); 537 if (rc < 0) { 538 char s[64]; 539 fdt_get_path(blob, fmnode, s, sizeof(s)); 540 printf("Could not add pointer property to node %s: %s\n", 541 s, fdt_strerror(rc)); 542 return; 543 } 544 } 545 } 546 #else 547 #define fdt_fixup_fman_firmware(x) 548 #endif 549 550 #if defined(CONFIG_PPC_P4080) 551 static void fdt_fixup_usb(void *fdt) 552 { 553 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 554 u32 rcwsr11 = in_be32(&gur->rcwsr[11]); 555 int off; 556 557 off = fdt_node_offset_by_compatible(fdt, -1, "fsl,mpc85xx-usb2-mph"); 558 if ((rcwsr11 & FSL_CORENET_RCWSR11_EC1) != 559 FSL_CORENET_RCWSR11_EC1_FM1_USB1) 560 fdt_status_disabled(fdt, off); 561 562 off = fdt_node_offset_by_compatible(fdt, -1, "fsl,mpc85xx-usb2-dr"); 563 if ((rcwsr11 & FSL_CORENET_RCWSR11_EC2) != 564 FSL_CORENET_RCWSR11_EC2_USB2) 565 fdt_status_disabled(fdt, off); 566 } 567 #else 568 #define fdt_fixup_usb(x) 569 #endif 570 571 void ft_cpu_setup(void *blob, bd_t *bd) 572 { 573 int off; 574 int val; 575 sys_info_t sysinfo; 576 577 /* delete crypto node if not on an E-processor */ 578 if (!IS_E_PROCESSOR(get_svr())) 579 fdt_fixup_crypto_node(blob, 0); 580 581 fdt_fixup_ethernet(blob); 582 583 fdt_add_enet_stashing(blob); 584 585 do_fixup_by_prop_u32(blob, "device_type", "cpu", 4, 586 "timebase-frequency", get_tbclk(), 1); 587 do_fixup_by_prop_u32(blob, "device_type", "cpu", 4, 588 "bus-frequency", bd->bi_busfreq, 1); 589 get_sys_info(&sysinfo); 590 off = fdt_node_offset_by_prop_value(blob, -1, "device_type", "cpu", 4); 591 while (off != -FDT_ERR_NOTFOUND) { 592 u32 *reg = (u32 *)fdt_getprop(blob, off, "reg", 0); 593 val = cpu_to_fdt32(sysinfo.freqProcessor[*reg]); 594 fdt_setprop(blob, off, "clock-frequency", &val, 4); 595 off = fdt_node_offset_by_prop_value(blob, off, "device_type", 596 "cpu", 4); 597 } 598 do_fixup_by_prop_u32(blob, "device_type", "soc", 4, 599 "bus-frequency", bd->bi_busfreq, 1); 600 601 do_fixup_by_compat_u32(blob, "fsl,pq3-localbus", 602 "bus-frequency", gd->lbc_clk, 1); 603 do_fixup_by_compat_u32(blob, "fsl,elbc", 604 "bus-frequency", gd->lbc_clk, 1); 605 #ifdef CONFIG_QE 606 ft_qe_setup(blob); 607 ft_fixup_qe_snum(blob); 608 #endif 609 610 fdt_fixup_fman_firmware(blob); 611 612 #ifdef CONFIG_SYS_NS16550 613 do_fixup_by_compat_u32(blob, "ns16550", 614 "clock-frequency", CONFIG_SYS_NS16550_CLK, 1); 615 #endif 616 617 #ifdef CONFIG_CPM2 618 do_fixup_by_compat_u32(blob, "fsl,cpm2-scc-uart", 619 "current-speed", bd->bi_baudrate, 1); 620 621 do_fixup_by_compat_u32(blob, "fsl,cpm2-brg", 622 "clock-frequency", bd->bi_brgfreq, 1); 623 #endif 624 625 #ifdef CONFIG_FSL_CORENET 626 do_fixup_by_compat_u32(blob, "fsl,qoriq-clockgen-1.0", 627 "clock-frequency", CONFIG_SYS_CLK_FREQ, 1); 628 #endif 629 630 fdt_fixup_memory(blob, (u64)bd->bi_memstart, (u64)bd->bi_memsize); 631 632 #ifdef CONFIG_MP 633 ft_fixup_cpu(blob, (u64)bd->bi_memstart + (u64)bd->bi_memsize); 634 ft_fixup_num_cores(blob); 635 #endif 636 637 ft_fixup_cache(blob); 638 639 #if defined(CONFIG_FSL_ESDHC) 640 fdt_fixup_esdhc(blob, bd); 641 #endif 642 643 ft_fixup_dpaa_clks(blob); 644 645 #if defined(CONFIG_SYS_BMAN_MEM_PHYS) 646 fdt_portal(blob, "fsl,bman-portal", "bman-portals", 647 (u64)CONFIG_SYS_BMAN_MEM_PHYS, 648 CONFIG_SYS_BMAN_MEM_SIZE); 649 fdt_fixup_bportals(blob); 650 #endif 651 652 #if defined(CONFIG_SYS_QMAN_MEM_PHYS) 653 fdt_portal(blob, "fsl,qman-portal", "qman-portals", 654 (u64)CONFIG_SYS_QMAN_MEM_PHYS, 655 CONFIG_SYS_QMAN_MEM_SIZE); 656 657 fdt_fixup_qportals(blob); 658 #endif 659 660 #ifdef CONFIG_SYS_SRIO 661 ft_srio_setup(blob); 662 #endif 663 664 /* 665 * system-clock = CCB clock/2 666 * Here gd->bus_clk = CCB clock 667 * We are using the system clock as 1588 Timer reference 668 * clock source select 669 */ 670 do_fixup_by_compat_u32(blob, "fsl,gianfar-ptp-timer", 671 "timer-frequency", gd->bus_clk/2, 1); 672 673 /* 674 * clock-freq should change to clock-frequency and 675 * flexcan-v1.0 should change to p1010-flexcan respectively 676 * in the future. 677 */ 678 do_fixup_by_compat_u32(blob, "fsl,flexcan-v1.0", 679 "clock_freq", gd->bus_clk/2, 1); 680 681 do_fixup_by_compat_u32(blob, "fsl,flexcan-v1.0", 682 "clock-frequency", gd->bus_clk/2, 1); 683 684 do_fixup_by_compat_u32(blob, "fsl,p1010-flexcan", 685 "clock-frequency", gd->bus_clk/2, 1); 686 687 fdt_fixup_usb(blob); 688 } 689 690 /* 691 * For some CCSR devices, we only have the virtual address, not the physical 692 * address. This is because we map CCSR as a whole, so we typically don't need 693 * a macro for the physical address of any device within CCSR. In this case, 694 * we calculate the physical address of that device using it's the difference 695 * between the virtual address of the device and the virtual address of the 696 * beginning of CCSR. 697 */ 698 #define CCSR_VIRT_TO_PHYS(x) \ 699 (CONFIG_SYS_CCSRBAR_PHYS + ((x) - CONFIG_SYS_CCSRBAR)) 700 701 static void msg(const char *name, uint64_t uaddr, uint64_t daddr) 702 { 703 printf("Warning: U-Boot configured %s at address %llx,\n" 704 "but the device tree has it at %llx\n", name, uaddr, daddr); 705 } 706 707 /* 708 * Verify the device tree 709 * 710 * This function compares several CONFIG_xxx macros that contain physical 711 * addresses with the corresponding nodes in the device tree, to see if 712 * the physical addresses are all correct. For example, if 713 * CONFIG_SYS_NS16550_COM1 is defined, then it contains the virtual address 714 * of the first UART. We convert this to a physical address and compare 715 * that with the physical address of the first ns16550-compatible node 716 * in the device tree. If they don't match, then we display a warning. 717 * 718 * Returns 1 on success, 0 on failure 719 */ 720 int ft_verify_fdt(void *fdt) 721 { 722 uint64_t addr = 0; 723 int aliases; 724 int off; 725 726 /* First check the CCSR base address */ 727 off = fdt_node_offset_by_prop_value(fdt, -1, "device_type", "soc", 4); 728 if (off > 0) 729 addr = fdt_get_base_address(fdt, off); 730 731 if (!addr) { 732 printf("Warning: could not determine base CCSR address in " 733 "device tree\n"); 734 /* No point in checking anything else */ 735 return 0; 736 } 737 738 if (addr != CONFIG_SYS_CCSRBAR_PHYS) { 739 msg("CCSR", CONFIG_SYS_CCSRBAR_PHYS, addr); 740 /* No point in checking anything else */ 741 return 0; 742 } 743 744 /* 745 * Check some nodes via aliases. We assume that U-Boot and the device 746 * tree enumerate the devices equally. E.g. the first serial port in 747 * U-Boot is the same as "serial0" in the device tree. 748 */ 749 aliases = fdt_path_offset(fdt, "/aliases"); 750 if (aliases > 0) { 751 #ifdef CONFIG_SYS_NS16550_COM1 752 if (!fdt_verify_alias_address(fdt, aliases, "serial0", 753 CCSR_VIRT_TO_PHYS(CONFIG_SYS_NS16550_COM1))) 754 return 0; 755 #endif 756 757 #ifdef CONFIG_SYS_NS16550_COM2 758 if (!fdt_verify_alias_address(fdt, aliases, "serial1", 759 CCSR_VIRT_TO_PHYS(CONFIG_SYS_NS16550_COM2))) 760 return 0; 761 #endif 762 } 763 764 /* 765 * The localbus node is typically a root node, even though the lbc 766 * controller is part of CCSR. If we were to put the lbc node under 767 * the SOC node, then the 'ranges' property in the lbc node would 768 * translate through the 'ranges' property of the parent SOC node, and 769 * we don't want that. Since it's a separate node, it's possible for 770 * the 'reg' property to be wrong, so check it here. For now, we 771 * only check for "fsl,elbc" nodes. 772 */ 773 #ifdef CONFIG_SYS_LBC_ADDR 774 off = fdt_node_offset_by_compatible(fdt, -1, "fsl,elbc"); 775 if (off > 0) { 776 const u32 *reg = fdt_getprop(fdt, off, "reg", NULL); 777 if (reg) { 778 uint64_t uaddr = CCSR_VIRT_TO_PHYS(CONFIG_SYS_LBC_ADDR); 779 780 addr = fdt_translate_address(fdt, off, reg); 781 if (uaddr != addr) { 782 msg("the localbus", uaddr, addr); 783 return 0; 784 } 785 } 786 } 787 #endif 788 789 return 1; 790 } 791