1 /* 2 * Copyright 2004, 2007-2011 Freescale Semiconductor, Inc. 3 * 4 * (C) Copyright 2003 Motorola Inc. 5 * Xianghua Xiao, (X.Xiao@motorola.com) 6 * 7 * (C) Copyright 2000 8 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 9 * 10 * See file CREDITS for list of people who contributed to this 11 * project. 12 * 13 * This program is free software; you can redistribute it and/or 14 * modify it under the terms of the GNU General Public License as 15 * published by the Free Software Foundation; either version 2 of 16 * the License, or (at your option) any later version. 17 * 18 * This program is distributed in the hope that it will be useful, 19 * but WITHOUT ANY WARRANTY; without even the implied warranty of 20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 21 * GNU General Public License for more details. 22 * 23 * You should have received a copy of the GNU General Public License 24 * along with this program; if not, write to the Free Software 25 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 26 * MA 02111-1307 USA 27 */ 28 29 #include <common.h> 30 #include <ppc_asm.tmpl> 31 #include <linux/compiler.h> 32 #include <asm/processor.h> 33 #include <asm/io.h> 34 35 DECLARE_GLOBAL_DATA_PTR; 36 37 /* --------------------------------------------------------------- */ 38 39 void get_sys_info (sys_info_t * sysInfo) 40 { 41 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 42 #ifdef CONFIG_FSL_IFC 43 struct fsl_ifc *ifc_regs = (void *)CONFIG_SYS_IFC_ADDR; 44 u32 ccr; 45 #endif 46 #ifdef CONFIG_FSL_CORENET 47 volatile ccsr_clk_t *clk = (void *)(CONFIG_SYS_FSL_CORENET_CLK_ADDR); 48 unsigned int cpu; 49 50 const u8 core_cplx_PLL[16] = { 51 [ 0] = 0, /* CC1 PPL / 1 */ 52 [ 1] = 0, /* CC1 PPL / 2 */ 53 [ 2] = 0, /* CC1 PPL / 4 */ 54 [ 4] = 1, /* CC2 PPL / 1 */ 55 [ 5] = 1, /* CC2 PPL / 2 */ 56 [ 6] = 1, /* CC2 PPL / 4 */ 57 [ 8] = 2, /* CC3 PPL / 1 */ 58 [ 9] = 2, /* CC3 PPL / 2 */ 59 [10] = 2, /* CC3 PPL / 4 */ 60 [12] = 3, /* CC4 PPL / 1 */ 61 [13] = 3, /* CC4 PPL / 2 */ 62 [14] = 3, /* CC4 PPL / 4 */ 63 }; 64 65 const u8 core_cplx_PLL_div[16] = { 66 [ 0] = 1, /* CC1 PPL / 1 */ 67 [ 1] = 2, /* CC1 PPL / 2 */ 68 [ 2] = 4, /* CC1 PPL / 4 */ 69 [ 4] = 1, /* CC2 PPL / 1 */ 70 [ 5] = 2, /* CC2 PPL / 2 */ 71 [ 6] = 4, /* CC2 PPL / 4 */ 72 [ 8] = 1, /* CC3 PPL / 1 */ 73 [ 9] = 2, /* CC3 PPL / 2 */ 74 [10] = 4, /* CC3 PPL / 4 */ 75 [12] = 1, /* CC4 PPL / 1 */ 76 [13] = 2, /* CC4 PPL / 2 */ 77 [14] = 4, /* CC4 PPL / 4 */ 78 }; 79 uint lcrr_div, i, freqCC_PLL[4], rcw_tmp; 80 uint ratio[4]; 81 unsigned long sysclk = CONFIG_SYS_CLK_FREQ; 82 uint mem_pll_rat; 83 84 sysInfo->freqSystemBus = sysclk; 85 sysInfo->freqDDRBus = sysclk; 86 87 sysInfo->freqSystemBus *= (in_be32(&gur->rcwsr[0]) >> 25) & 0x1f; 88 mem_pll_rat = (in_be32(&gur->rcwsr[0]) >> 89 FSL_CORENET_RCWSR0_MEM_PLL_RAT_SHIFT) 90 & FSL_CORENET_RCWSR0_MEM_PLL_RAT_MASK; 91 if (mem_pll_rat > 2) 92 sysInfo->freqDDRBus *= mem_pll_rat; 93 else 94 sysInfo->freqDDRBus = sysInfo->freqSystemBus * mem_pll_rat; 95 96 ratio[0] = (in_be32(&clk->pllc1gsr) >> 1) & 0x3f; 97 ratio[1] = (in_be32(&clk->pllc2gsr) >> 1) & 0x3f; 98 ratio[2] = (in_be32(&clk->pllc3gsr) >> 1) & 0x3f; 99 ratio[3] = (in_be32(&clk->pllc4gsr) >> 1) & 0x3f; 100 for (i = 0; i < 4; i++) { 101 if (ratio[i] > 4) 102 freqCC_PLL[i] = sysclk * ratio[i]; 103 else 104 freqCC_PLL[i] = sysInfo->freqSystemBus * ratio[i]; 105 } 106 rcw_tmp = in_be32(&gur->rcwsr[3]); 107 for_each_cpu(i, cpu, cpu_numcores(), cpu_mask()) { 108 u32 c_pll_sel = (in_be32(&clk->clkc0csr + cpu*8) >> 27) & 0xf; 109 u32 cplx_pll = core_cplx_PLL[c_pll_sel]; 110 111 sysInfo->freqProcessor[cpu] = 112 freqCC_PLL[cplx_pll] / core_cplx_PLL_div[c_pll_sel]; 113 } 114 115 #define PME_CLK_SEL 0x80000000 116 #define FM1_CLK_SEL 0x40000000 117 #define FM2_CLK_SEL 0x20000000 118 #define HWA_ASYNC_DIV 0x04000000 119 #if (CONFIG_SYS_FSL_NUM_CC_PLLS == 2) 120 #define HWA_CC_PLL 1 121 #elif (CONFIG_SYS_FSL_NUM_CC_PLLS == 3) 122 #define HWA_CC_PLL 2 123 #elif (CONFIG_SYS_FSL_NUM_CC_PLLS == 4) 124 #define HWA_CC_PLL 2 125 #else 126 #error CONFIG_SYS_FSL_NUM_CC_PLLS not set or unknown case 127 #endif 128 rcw_tmp = in_be32(&gur->rcwsr[7]); 129 130 #ifdef CONFIG_SYS_DPAA_PME 131 if (rcw_tmp & PME_CLK_SEL) { 132 if (rcw_tmp & HWA_ASYNC_DIV) 133 sysInfo->freqPME = freqCC_PLL[HWA_CC_PLL] / 4; 134 else 135 sysInfo->freqPME = freqCC_PLL[HWA_CC_PLL] / 2; 136 } else { 137 sysInfo->freqPME = sysInfo->freqSystemBus / 2; 138 } 139 #endif 140 141 #ifdef CONFIG_SYS_DPAA_FMAN 142 if (rcw_tmp & FM1_CLK_SEL) { 143 if (rcw_tmp & HWA_ASYNC_DIV) 144 sysInfo->freqFMan[0] = freqCC_PLL[HWA_CC_PLL] / 4; 145 else 146 sysInfo->freqFMan[0] = freqCC_PLL[HWA_CC_PLL] / 2; 147 } else { 148 sysInfo->freqFMan[0] = sysInfo->freqSystemBus / 2; 149 } 150 #if (CONFIG_SYS_NUM_FMAN) == 2 151 if (rcw_tmp & FM2_CLK_SEL) { 152 if (rcw_tmp & HWA_ASYNC_DIV) 153 sysInfo->freqFMan[1] = freqCC_PLL[HWA_CC_PLL] / 4; 154 else 155 sysInfo->freqFMan[1] = freqCC_PLL[HWA_CC_PLL] / 2; 156 } else { 157 sysInfo->freqFMan[1] = sysInfo->freqSystemBus / 2; 158 } 159 #endif 160 #endif 161 162 #else 163 uint plat_ratio,e500_ratio,half_freqSystemBus; 164 #if defined(CONFIG_FSL_LBC) 165 uint lcrr_div; 166 #endif 167 int i; 168 #ifdef CONFIG_QE 169 __maybe_unused u32 qe_ratio; 170 #endif 171 172 plat_ratio = (gur->porpllsr) & 0x0000003e; 173 plat_ratio >>= 1; 174 sysInfo->freqSystemBus = plat_ratio * CONFIG_SYS_CLK_FREQ; 175 176 /* Divide before multiply to avoid integer 177 * overflow for processor speeds above 2GHz */ 178 half_freqSystemBus = sysInfo->freqSystemBus/2; 179 for (i = 0; i < cpu_numcores(); i++) { 180 e500_ratio = ((gur->porpllsr) >> (i * 8 + 16)) & 0x3f; 181 sysInfo->freqProcessor[i] = e500_ratio * half_freqSystemBus; 182 } 183 184 /* Note: freqDDRBus is the MCLK frequency, not the data rate. */ 185 sysInfo->freqDDRBus = sysInfo->freqSystemBus; 186 187 #ifdef CONFIG_DDR_CLK_FREQ 188 { 189 u32 ddr_ratio = ((gur->porpllsr) & MPC85xx_PORPLLSR_DDR_RATIO) 190 >> MPC85xx_PORPLLSR_DDR_RATIO_SHIFT; 191 if (ddr_ratio != 0x7) 192 sysInfo->freqDDRBus = ddr_ratio * CONFIG_DDR_CLK_FREQ; 193 } 194 #endif 195 196 #ifdef CONFIG_QE 197 #if defined(CONFIG_P1012) || defined(CONFIG_P1021) || defined(CONFIG_P1025) 198 sysInfo->freqQE = sysInfo->freqSystemBus; 199 #else 200 qe_ratio = ((gur->porpllsr) & MPC85xx_PORPLLSR_QE_RATIO) 201 >> MPC85xx_PORPLLSR_QE_RATIO_SHIFT; 202 sysInfo->freqQE = qe_ratio * CONFIG_SYS_CLK_FREQ; 203 #endif 204 #endif 205 206 #ifdef CONFIG_SYS_DPAA_FMAN 207 sysInfo->freqFMan[0] = sysInfo->freqSystemBus; 208 #endif 209 210 #endif /* CONFIG_FSL_CORENET */ 211 212 #if defined(CONFIG_FSL_LBC) 213 #if defined(CONFIG_SYS_LBC_LCRR) 214 /* We will program LCRR to this value later */ 215 lcrr_div = CONFIG_SYS_LBC_LCRR & LCRR_CLKDIV; 216 #else 217 lcrr_div = in_be32(&(LBC_BASE_ADDR)->lcrr) & LCRR_CLKDIV; 218 #endif 219 if (lcrr_div == 2 || lcrr_div == 4 || lcrr_div == 8) { 220 #if defined(CONFIG_FSL_CORENET) 221 /* If this is corenet based SoC, bit-representation 222 * for four times the clock divider values. 223 */ 224 lcrr_div *= 4; 225 #elif !defined(CONFIG_MPC8540) && !defined(CONFIG_MPC8541) && \ 226 !defined(CONFIG_MPC8555) && !defined(CONFIG_MPC8560) 227 /* 228 * Yes, the entire PQ38 family use the same 229 * bit-representation for twice the clock divider values. 230 */ 231 lcrr_div *= 2; 232 #endif 233 sysInfo->freqLocalBus = sysInfo->freqSystemBus / lcrr_div; 234 } else { 235 /* In case anyone cares what the unknown value is */ 236 sysInfo->freqLocalBus = lcrr_div; 237 } 238 #endif 239 240 #if defined(CONFIG_FSL_IFC) 241 ccr = in_be32(&ifc_regs->ifc_ccr); 242 ccr = ((ccr & IFC_CCR_CLK_DIV_MASK) >> IFC_CCR_CLK_DIV_SHIFT) + 1; 243 244 sysInfo->freqLocalBus = sysInfo->freqSystemBus / ccr; 245 #endif 246 } 247 248 249 int get_clocks (void) 250 { 251 sys_info_t sys_info; 252 #ifdef CONFIG_MPC8544 253 volatile ccsr_gur_t *gur = (void *) CONFIG_SYS_MPC85xx_GUTS_ADDR; 254 #endif 255 #if defined(CONFIG_CPM2) 256 volatile ccsr_cpm_t *cpm = (ccsr_cpm_t *)CONFIG_SYS_MPC85xx_CPM_ADDR; 257 uint sccr, dfbrg; 258 259 /* set VCO = 4 * BRG */ 260 cpm->im_cpm_intctl.sccr &= 0xfffffffc; 261 sccr = cpm->im_cpm_intctl.sccr; 262 dfbrg = (sccr & SCCR_DFBRG_MSK) >> SCCR_DFBRG_SHIFT; 263 #endif 264 get_sys_info (&sys_info); 265 gd->cpu_clk = sys_info.freqProcessor[0]; 266 gd->bus_clk = sys_info.freqSystemBus; 267 gd->mem_clk = sys_info.freqDDRBus; 268 gd->lbc_clk = sys_info.freqLocalBus; 269 270 #ifdef CONFIG_QE 271 gd->qe_clk = sys_info.freqQE; 272 gd->brg_clk = gd->qe_clk / 2; 273 #endif 274 /* 275 * The base clock for I2C depends on the actual SOC. Unfortunately, 276 * there is no pattern that can be used to determine the frequency, so 277 * the only choice is to look up the actual SOC number and use the value 278 * for that SOC. This information is taken from application note 279 * AN2919. 280 */ 281 #if defined(CONFIG_MPC8540) || defined(CONFIG_MPC8541) || \ 282 defined(CONFIG_MPC8560) || defined(CONFIG_MPC8555) 283 gd->i2c1_clk = sys_info.freqSystemBus; 284 #elif defined(CONFIG_MPC8544) 285 /* 286 * On the 8544, the I2C clock is the same as the SEC clock. This can be 287 * either CCB/2 or CCB/3, depending on the value of cfg_sec_freq. See 288 * 4.4.3.3 of the 8544 RM. Note that this might actually work for all 289 * 85xx, but only the 8544 has cfg_sec_freq, so it's unknown if the 290 * PORDEVSR2_SEC_CFG bit is 0 on all 85xx boards that are not an 8544. 291 */ 292 if (gur->pordevsr2 & MPC85xx_PORDEVSR2_SEC_CFG) 293 gd->i2c1_clk = sys_info.freqSystemBus / 3; 294 else 295 gd->i2c1_clk = sys_info.freqSystemBus / 2; 296 #else 297 /* Most 85xx SOCs use CCB/2, so this is the default behavior. */ 298 gd->i2c1_clk = sys_info.freqSystemBus / 2; 299 #endif 300 gd->i2c2_clk = gd->i2c1_clk; 301 302 #if defined(CONFIG_FSL_ESDHC) 303 #if defined(CONFIG_MPC8569) || defined(CONFIG_P1010) ||\ 304 defined(CONFIG_P1014) 305 gd->sdhc_clk = gd->bus_clk; 306 #else 307 gd->sdhc_clk = gd->bus_clk / 2; 308 #endif 309 #endif /* defined(CONFIG_FSL_ESDHC) */ 310 311 #if defined(CONFIG_CPM2) 312 gd->vco_out = 2*sys_info.freqSystemBus; 313 gd->cpm_clk = gd->vco_out / 2; 314 gd->scc_clk = gd->vco_out / 4; 315 gd->brg_clk = gd->vco_out / (1 << (2 * (dfbrg + 1))); 316 #endif 317 318 if(gd->cpu_clk != 0) return (0); 319 else return (1); 320 } 321 322 323 /******************************************** 324 * get_bus_freq 325 * return system bus freq in Hz 326 *********************************************/ 327 ulong get_bus_freq (ulong dummy) 328 { 329 return gd->bus_clk; 330 } 331 332 /******************************************** 333 * get_ddr_freq 334 * return ddr bus freq in Hz 335 *********************************************/ 336 ulong get_ddr_freq (ulong dummy) 337 { 338 return gd->mem_clk; 339 } 340