1 /* 2 * Copyright 2004,2007-2011 Freescale Semiconductor, Inc. 3 * (C) Copyright 2002, 2003 Motorola Inc. 4 * Xianghua Xiao (X.Xiao@motorola.com) 5 * 6 * (C) Copyright 2000 7 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 8 * 9 * See file CREDITS for list of people who contributed to this 10 * project. 11 * 12 * This program is free software; you can redistribute it and/or 13 * modify it under the terms of the GNU General Public License as 14 * published by the Free Software Foundation; either version 2 of 15 * the License, or (at your option) any later version. 16 * 17 * This program is distributed in the hope that it will be useful, 18 * but WITHOUT ANY WARRANTY; without even the implied warranty of 19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 20 * GNU General Public License for more details. 21 * 22 * You should have received a copy of the GNU General Public License 23 * along with this program; if not, write to the Free Software 24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 25 * MA 02111-1307 USA 26 */ 27 28 #include <config.h> 29 #include <common.h> 30 #include <watchdog.h> 31 #include <command.h> 32 #include <fsl_esdhc.h> 33 #include <asm/cache.h> 34 #include <asm/io.h> 35 #include <asm/mmu.h> 36 #include <asm/fsl_ifc.h> 37 #include <asm/fsl_law.h> 38 #include <asm/fsl_lbc.h> 39 #include <post.h> 40 #include <asm/processor.h> 41 #include <asm/fsl_ddr_sdram.h> 42 43 DECLARE_GLOBAL_DATA_PTR; 44 45 /* 46 * Default board reset function 47 */ 48 static void 49 __board_reset(void) 50 { 51 /* Do nothing */ 52 } 53 void board_reset(void) __attribute__((weak, alias("__board_reset"))); 54 55 int checkcpu (void) 56 { 57 sys_info_t sysinfo; 58 uint pvr, svr; 59 uint ver; 60 uint major, minor; 61 struct cpu_type *cpu; 62 char buf1[32], buf2[32]; 63 #if defined(CONFIG_DDR_CLK_FREQ) || defined(CONFIG_FSL_CORENET) 64 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 65 #endif /* CONFIG_FSL_CORENET */ 66 #ifdef CONFIG_DDR_CLK_FREQ 67 u32 ddr_ratio = ((gur->porpllsr) & MPC85xx_PORPLLSR_DDR_RATIO) 68 >> MPC85xx_PORPLLSR_DDR_RATIO_SHIFT; 69 #else 70 #ifdef CONFIG_FSL_CORENET 71 u32 ddr_sync = ((gur->rcwsr[5]) & FSL_CORENET_RCWSR5_DDR_SYNC) 72 >> FSL_CORENET_RCWSR5_DDR_SYNC_SHIFT; 73 #else 74 u32 ddr_ratio = 0; 75 #endif /* CONFIG_FSL_CORENET */ 76 #endif /* CONFIG_DDR_CLK_FREQ */ 77 unsigned int i, core, nr_cores = cpu_numcores(); 78 u32 mask = cpu_mask(); 79 80 svr = get_svr(); 81 major = SVR_MAJ(svr); 82 minor = SVR_MIN(svr); 83 84 if (cpu_numcores() > 1) { 85 #ifndef CONFIG_MP 86 puts("Unicore software on multiprocessor system!!\n" 87 "To enable mutlticore build define CONFIG_MP\n"); 88 #endif 89 volatile ccsr_pic_t *pic = (void *)(CONFIG_SYS_MPC8xxx_PIC_ADDR); 90 printf("CPU%d: ", pic->whoami); 91 } else { 92 puts("CPU: "); 93 } 94 95 cpu = gd->cpu; 96 97 puts(cpu->name); 98 if (IS_E_PROCESSOR(svr)) 99 puts("E"); 100 101 printf(", Version: %d.%d, (0x%08x)\n", major, minor, svr); 102 103 pvr = get_pvr(); 104 ver = PVR_VER(pvr); 105 major = PVR_MAJ(pvr); 106 minor = PVR_MIN(pvr); 107 108 printf("Core: "); 109 switch(ver) { 110 case PVR_VER_E500_V1: 111 case PVR_VER_E500_V2: 112 puts("E500"); 113 break; 114 case PVR_VER_E500MC: 115 puts("E500MC"); 116 break; 117 case PVR_VER_E5500: 118 puts("E5500"); 119 break; 120 case PVR_VER_E6500: 121 puts("E6500"); 122 break; 123 default: 124 puts("Unknown"); 125 break; 126 } 127 128 printf(", Version: %d.%d, (0x%08x)\n", major, minor, pvr); 129 130 if (nr_cores > CONFIG_MAX_CPUS) { 131 panic("\nUnexpected number of cores: %d, max is %d\n", 132 nr_cores, CONFIG_MAX_CPUS); 133 } 134 135 get_sys_info(&sysinfo); 136 137 puts("Clock Configuration:"); 138 for_each_cpu(i, core, nr_cores, mask) { 139 if (!(i & 3)) 140 printf ("\n "); 141 printf("CPU%d:%-4s MHz, ", core, 142 strmhz(buf1, sysinfo.freqProcessor[core])); 143 } 144 printf("\n CCB:%-4s MHz,\n", strmhz(buf1, sysinfo.freqSystemBus)); 145 146 #ifdef CONFIG_FSL_CORENET 147 if (ddr_sync == 1) { 148 printf(" DDR:%-4s MHz (%s MT/s data rate) " 149 "(Synchronous), ", 150 strmhz(buf1, sysinfo.freqDDRBus/2), 151 strmhz(buf2, sysinfo.freqDDRBus)); 152 } else { 153 printf(" DDR:%-4s MHz (%s MT/s data rate) " 154 "(Asynchronous), ", 155 strmhz(buf1, sysinfo.freqDDRBus/2), 156 strmhz(buf2, sysinfo.freqDDRBus)); 157 } 158 #else 159 switch (ddr_ratio) { 160 case 0x0: 161 printf(" DDR:%-4s MHz (%s MT/s data rate), ", 162 strmhz(buf1, sysinfo.freqDDRBus/2), 163 strmhz(buf2, sysinfo.freqDDRBus)); 164 break; 165 case 0x7: 166 printf(" DDR:%-4s MHz (%s MT/s data rate) " 167 "(Synchronous), ", 168 strmhz(buf1, sysinfo.freqDDRBus/2), 169 strmhz(buf2, sysinfo.freqDDRBus)); 170 break; 171 default: 172 printf(" DDR:%-4s MHz (%s MT/s data rate) " 173 "(Asynchronous), ", 174 strmhz(buf1, sysinfo.freqDDRBus/2), 175 strmhz(buf2, sysinfo.freqDDRBus)); 176 break; 177 } 178 #endif 179 180 #if defined(CONFIG_FSL_LBC) 181 if (sysinfo.freqLocalBus > LCRR_CLKDIV) { 182 printf("LBC:%-4s MHz\n", strmhz(buf1, sysinfo.freqLocalBus)); 183 } else { 184 printf("LBC: unknown (LCRR[CLKDIV] = 0x%02lx)\n", 185 sysinfo.freqLocalBus); 186 } 187 #endif 188 189 #if defined(CONFIG_FSL_IFC) 190 printf("IFC:%-4s MHz\n", strmhz(buf1, sysinfo.freqLocalBus)); 191 #endif 192 193 #ifdef CONFIG_CPM2 194 printf("CPM: %s MHz\n", strmhz(buf1, sysinfo.freqSystemBus)); 195 #endif 196 197 #ifdef CONFIG_QE 198 printf(" QE:%-4s MHz\n", strmhz(buf1, sysinfo.freqQE)); 199 #endif 200 201 #ifdef CONFIG_SYS_DPAA_FMAN 202 for (i = 0; i < CONFIG_SYS_NUM_FMAN; i++) { 203 printf(" FMAN%d: %s MHz\n", i + 1, 204 strmhz(buf1, sysinfo.freqFMan[i])); 205 } 206 #endif 207 208 #ifdef CONFIG_SYS_DPAA_PME 209 printf(" PME: %s MHz\n", strmhz(buf1, sysinfo.freqPME)); 210 #endif 211 212 puts("L1: D-cache 32 kB enabled\n I-cache 32 kB enabled\n"); 213 214 return 0; 215 } 216 217 218 /* ------------------------------------------------------------------------- */ 219 220 int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) 221 { 222 /* Everything after the first generation of PQ3 parts has RSTCR */ 223 #if defined(CONFIG_MPC8540) || defined(CONFIG_MPC8541) || \ 224 defined(CONFIG_MPC8555) || defined(CONFIG_MPC8560) 225 unsigned long val, msr; 226 227 /* 228 * Initiate hard reset in debug control register DBCR0 229 * Make sure MSR[DE] = 1. This only resets the core. 230 */ 231 msr = mfmsr (); 232 msr |= MSR_DE; 233 mtmsr (msr); 234 235 val = mfspr(DBCR0); 236 val |= 0x70000000; 237 mtspr(DBCR0,val); 238 #else 239 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 240 241 /* Attempt board-specific reset */ 242 board_reset(); 243 244 /* Next try asserting HRESET_REQ */ 245 out_be32(&gur->rstcr, 0x2); 246 udelay(100); 247 #endif 248 249 return 1; 250 } 251 252 253 /* 254 * Get timebase clock frequency 255 */ 256 #ifndef CONFIG_SYS_FSL_TBCLK_DIV 257 #define CONFIG_SYS_FSL_TBCLK_DIV 8 258 #endif 259 unsigned long get_tbclk (void) 260 { 261 unsigned long tbclk_div = CONFIG_SYS_FSL_TBCLK_DIV; 262 263 return (gd->bus_clk + (tbclk_div >> 1)) / tbclk_div; 264 } 265 266 267 #if defined(CONFIG_WATCHDOG) 268 void 269 watchdog_reset(void) 270 { 271 int re_enable = disable_interrupts(); 272 reset_85xx_watchdog(); 273 if (re_enable) enable_interrupts(); 274 } 275 276 void 277 reset_85xx_watchdog(void) 278 { 279 /* 280 * Clear TSR(WIS) bit by writing 1 281 */ 282 mtspr(SPRN_TSR, TSR_WIS); 283 } 284 #endif /* CONFIG_WATCHDOG */ 285 286 /* 287 * Initializes on-chip MMC controllers. 288 * to override, implement board_mmc_init() 289 */ 290 int cpu_mmc_init(bd_t *bis) 291 { 292 #ifdef CONFIG_FSL_ESDHC 293 return fsl_esdhc_mmc_init(bis); 294 #else 295 return 0; 296 #endif 297 } 298 299 /* 300 * Print out the state of various machine registers. 301 * Currently prints out LAWs, BR0/OR0 for LBC, CSPR/CSOR/Timing 302 * parameters for IFC and TLBs 303 */ 304 void mpc85xx_reginfo(void) 305 { 306 print_tlbcam(); 307 print_laws(); 308 #if defined(CONFIG_FSL_LBC) 309 print_lbc_regs(); 310 #endif 311 #ifdef CONFIG_FSL_IFC 312 print_ifc_regs(); 313 #endif 314 315 } 316 317 /* Common ddr init for non-corenet fsl 85xx platforms */ 318 #ifndef CONFIG_FSL_CORENET 319 #if defined(CONFIG_SYS_RAMBOOT) && !defined(CONFIG_SYS_INIT_L2_ADDR) 320 phys_size_t initdram(int board_type) 321 { 322 #if defined(CONFIG_SPD_EEPROM) || defined(CONFIG_DDR_SPD) 323 return fsl_ddr_sdram_size(); 324 #else 325 return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024; 326 #endif 327 } 328 #else /* CONFIG_SYS_RAMBOOT */ 329 phys_size_t initdram(int board_type) 330 { 331 phys_size_t dram_size = 0; 332 333 #if defined(CONFIG_SYS_FSL_ERRATUM_DDR_MSYNC_IN) 334 { 335 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 336 unsigned int x = 10; 337 unsigned int i; 338 339 /* 340 * Work around to stabilize DDR DLL 341 */ 342 out_be32(&gur->ddrdllcr, 0x81000000); 343 asm("sync;isync;msync"); 344 udelay(200); 345 while (in_be32(&gur->ddrdllcr) != 0x81000100) { 346 setbits_be32(&gur->devdisr, 0x00010000); 347 for (i = 0; i < x; i++) 348 ; 349 clrbits_be32(&gur->devdisr, 0x00010000); 350 x++; 351 } 352 } 353 #endif 354 355 #if defined(CONFIG_SPD_EEPROM) || \ 356 defined(CONFIG_DDR_SPD) || \ 357 defined(CONFIG_SYS_DDR_RAW_TIMING) 358 dram_size = fsl_ddr_sdram(); 359 #else 360 dram_size = fixed_sdram(); 361 #endif 362 dram_size = setup_ddr_tlbs(dram_size / 0x100000); 363 dram_size *= 0x100000; 364 365 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) 366 /* 367 * Initialize and enable DDR ECC. 368 */ 369 ddr_enable_ecc(dram_size); 370 #endif 371 372 #if defined(CONFIG_FSL_LBC) 373 /* Some boards also have sdram on the lbc */ 374 lbc_sdram_init(); 375 #endif 376 377 debug("DDR: "); 378 return dram_size; 379 } 380 #endif /* CONFIG_SYS_RAMBOOT */ 381 #endif 382 383 #if CONFIG_POST & CONFIG_SYS_POST_MEMORY 384 385 /* Board-specific functions defined in each board's ddr.c */ 386 void fsl_ddr_get_spd(generic_spd_eeprom_t *ctrl_dimms_spd, 387 unsigned int ctrl_num); 388 void read_tlbcam_entry(int idx, u32 *valid, u32 *tsize, unsigned long *epn, 389 phys_addr_t *rpn); 390 unsigned int 391 setup_ddr_tlbs_phys(phys_addr_t p_addr, unsigned int memsize_in_meg); 392 393 void clear_ddr_tlbs_phys(phys_addr_t p_addr, unsigned int memsize_in_meg); 394 395 static void dump_spd_ddr_reg(void) 396 { 397 int i, j, k, m; 398 u8 *p_8; 399 u32 *p_32; 400 ccsr_ddr_t *ddr[CONFIG_NUM_DDR_CONTROLLERS]; 401 generic_spd_eeprom_t 402 spd[CONFIG_NUM_DDR_CONTROLLERS][CONFIG_DIMM_SLOTS_PER_CTLR]; 403 404 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) 405 fsl_ddr_get_spd(spd[i], i); 406 407 puts("SPD data of all dimms (zero vaule is omitted)...\n"); 408 puts("Byte (hex) "); 409 k = 1; 410 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) { 411 for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) 412 printf("Dimm%d ", k++); 413 } 414 puts("\n"); 415 for (k = 0; k < sizeof(generic_spd_eeprom_t); k++) { 416 m = 0; 417 printf("%3d (0x%02x) ", k, k); 418 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) { 419 for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) { 420 p_8 = (u8 *) &spd[i][j]; 421 if (p_8[k]) { 422 printf("0x%02x ", p_8[k]); 423 m++; 424 } else 425 puts(" "); 426 } 427 } 428 if (m) 429 puts("\n"); 430 else 431 puts("\r"); 432 } 433 434 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) { 435 switch (i) { 436 case 0: 437 ddr[i] = (void *)CONFIG_SYS_MPC85xx_DDR_ADDR; 438 break; 439 #if defined(CONFIG_SYS_MPC85xx_DDR2_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 1) 440 case 1: 441 ddr[i] = (void *)CONFIG_SYS_MPC85xx_DDR2_ADDR; 442 break; 443 #endif 444 #if defined(CONFIG_SYS_MPC85xx_DDR3_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 2) 445 case 2: 446 ddr[i] = (void *)CONFIG_SYS_MPC85xx_DDR3_ADDR; 447 break; 448 #endif 449 #if defined(CONFIG_SYS_MPC85xx_DDR4_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 3) 450 case 3: 451 ddr[i] = (void *)CONFIG_SYS_MPC85xx_DDR4_ADDR; 452 break; 453 #endif 454 default: 455 printf("%s unexpected controller number = %u\n", 456 __func__, i); 457 return; 458 } 459 } 460 printf("DDR registers dump for all controllers " 461 "(zero vaule is omitted)...\n"); 462 puts("Offset (hex) "); 463 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) 464 printf(" Base + 0x%04x", (u32)ddr[i] & 0xFFFF); 465 puts("\n"); 466 for (k = 0; k < sizeof(ccsr_ddr_t)/4; k++) { 467 m = 0; 468 printf("%6d (0x%04x)", k * 4, k * 4); 469 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) { 470 p_32 = (u32 *) ddr[i]; 471 if (p_32[k]) { 472 printf(" 0x%08x", p_32[k]); 473 m++; 474 } else 475 puts(" "); 476 } 477 if (m) 478 puts("\n"); 479 else 480 puts("\r"); 481 } 482 puts("\n"); 483 } 484 485 /* invalid the TLBs for DDR and setup new ones to cover p_addr */ 486 static int reset_tlb(phys_addr_t p_addr, u32 size, phys_addr_t *phys_offset) 487 { 488 u32 vstart = CONFIG_SYS_DDR_SDRAM_BASE; 489 unsigned long epn; 490 u32 tsize, valid, ptr; 491 int ddr_esel; 492 493 clear_ddr_tlbs_phys(p_addr, size>>20); 494 495 /* Setup new tlb to cover the physical address */ 496 setup_ddr_tlbs_phys(p_addr, size>>20); 497 498 ptr = vstart; 499 ddr_esel = find_tlb_idx((void *)ptr, 1); 500 if (ddr_esel != -1) { 501 read_tlbcam_entry(ddr_esel, &valid, &tsize, &epn, phys_offset); 502 } else { 503 printf("TLB error in function %s\n", __func__); 504 return -1; 505 } 506 507 return 0; 508 } 509 510 /* 511 * slide the testing window up to test another area 512 * for 32_bit system, the maximum testable memory is limited to 513 * CONFIG_MAX_MEM_MAPPED 514 */ 515 int arch_memory_test_advance(u32 *vstart, u32 *size, phys_addr_t *phys_offset) 516 { 517 phys_addr_t test_cap, p_addr; 518 phys_size_t p_size = min(gd->ram_size, CONFIG_MAX_MEM_MAPPED); 519 520 #if !defined(CONFIG_PHYS_64BIT) || \ 521 !defined(CONFIG_SYS_INIT_RAM_ADDR_PHYS) || \ 522 (CONFIG_SYS_INIT_RAM_ADDR_PHYS < 0x100000000ull) 523 test_cap = p_size; 524 #else 525 test_cap = gd->ram_size; 526 #endif 527 p_addr = (*vstart) + (*size) + (*phys_offset); 528 if (p_addr < test_cap - 1) { 529 p_size = min(test_cap - p_addr, CONFIG_MAX_MEM_MAPPED); 530 if (reset_tlb(p_addr, p_size, phys_offset) == -1) 531 return -1; 532 *vstart = CONFIG_SYS_DDR_SDRAM_BASE; 533 *size = (u32) p_size; 534 printf("Testing 0x%08llx - 0x%08llx\n", 535 (u64)(*vstart) + (*phys_offset), 536 (u64)(*vstart) + (*phys_offset) + (*size) - 1); 537 } else 538 return 1; 539 540 return 0; 541 } 542 543 /* initialization for testing area */ 544 int arch_memory_test_prepare(u32 *vstart, u32 *size, phys_addr_t *phys_offset) 545 { 546 phys_size_t p_size = min(gd->ram_size, CONFIG_MAX_MEM_MAPPED); 547 548 *vstart = CONFIG_SYS_DDR_SDRAM_BASE; 549 *size = (u32) p_size; /* CONFIG_MAX_MEM_MAPPED < 4G */ 550 *phys_offset = 0; 551 552 #if !defined(CONFIG_PHYS_64BIT) || \ 553 !defined(CONFIG_SYS_INIT_RAM_ADDR_PHYS) || \ 554 (CONFIG_SYS_INIT_RAM_ADDR_PHYS < 0x100000000ull) 555 if (gd->ram_size > CONFIG_MAX_MEM_MAPPED) { 556 puts("Cannot test more than "); 557 print_size(CONFIG_MAX_MEM_MAPPED, 558 " without proper 36BIT support.\n"); 559 } 560 #endif 561 printf("Testing 0x%08llx - 0x%08llx\n", 562 (u64)(*vstart) + (*phys_offset), 563 (u64)(*vstart) + (*phys_offset) + (*size) - 1); 564 565 return 0; 566 } 567 568 /* invalid TLBs for DDR and remap as normal after testing */ 569 int arch_memory_test_cleanup(u32 *vstart, u32 *size, phys_addr_t *phys_offset) 570 { 571 unsigned long epn; 572 u32 tsize, valid, ptr; 573 phys_addr_t rpn = 0; 574 int ddr_esel; 575 576 /* disable the TLBs for this testing */ 577 ptr = *vstart; 578 579 while (ptr < (*vstart) + (*size)) { 580 ddr_esel = find_tlb_idx((void *)ptr, 1); 581 if (ddr_esel != -1) { 582 read_tlbcam_entry(ddr_esel, &valid, &tsize, &epn, &rpn); 583 disable_tlb(ddr_esel); 584 } 585 ptr += TSIZE_TO_BYTES(tsize); 586 } 587 588 puts("Remap DDR "); 589 setup_ddr_tlbs(gd->ram_size>>20); 590 puts("\n"); 591 592 return 0; 593 } 594 595 void arch_memory_failure_handle(void) 596 { 597 dump_spd_ddr_reg(); 598 } 599 #endif 600