xref: /rk3399_rockchip-uboot/arch/mips/cpu/start.S (revision af3971f81ac0fc344461cf86af682ecf1ebe18a8) 
1/*
2 *  Startup Code for MIPS32 CPU-core
3 *
4 *  Copyright (c) 2003	Wolfgang Denk <wd@denx.de>
5 *
6 * SPDX-License-Identifier:	GPL-2.0+
7 */
8
9#include <asm-offsets.h>
10#include <config.h>
11#include <asm/asm.h>
12#include <asm/regdef.h>
13#include <asm/mipsregs.h>
14
15#ifndef CONFIG_SYS_INIT_SP_ADDR
16#define CONFIG_SYS_INIT_SP_ADDR	(CONFIG_SYS_SDRAM_BASE + \
17				CONFIG_SYS_INIT_SP_OFFSET)
18#endif
19
20#ifdef CONFIG_32BIT
21# define MIPS_RELOC	3
22# define STATUS_SET	0
23#endif
24
25#ifdef CONFIG_64BIT
26# ifdef CONFIG_SYS_LITTLE_ENDIAN
27#  define MIPS64_R_INFO(ssym, r_type3, r_type2, r_type) \
28	(((r_type) << 24) | ((r_type2) << 16) | ((r_type3) << 8) | (ssym))
29# else
30#  define MIPS64_R_INFO(ssym, r_type3, r_type2, r_type) \
31	((r_type) | ((r_type2) << 8) | ((r_type3) << 16) | (ssym) << 24)
32# endif
33# define MIPS_RELOC	MIPS64_R_INFO(0x00, 0x00, 0x12, 0x03)
34# define STATUS_SET	ST0_KX
35#endif
36
37	/*
38	 * For the moment disable interrupts, mark the kernel mode and
39	 * set ST0_KX so that the CPU does not spit fire when using
40	 * 64-bit addresses.
41	 */
42	.macro	setup_c0_status set clr
43	.set	push
44	mfc0	t0, CP0_STATUS
45	or	t0, ST0_CU0 | \set | 0x1f | \clr
46	xor	t0, 0x1f | \clr
47	mtc0	t0, CP0_STATUS
48	.set	noreorder
49	sll	zero, 3				# ehb
50	.set	pop
51	.endm
52
53	.set noreorder
54
55ENTRY(_start)
56	/* U-Boot entry point */
57	b	reset
58	 nop
59
60#if defined(CONFIG_SYS_XWAY_EBU_BOOTCFG)
61	/*
62	 * Almost all Lantiq XWAY SoC devices have an external bus unit (EBU) to
63	 * access external NOR flashes. If the board boots from NOR flash the
64	 * internal BootROM does a blind read at address 0xB0000010 to read the
65	 * initial configuration for that EBU in order to access the flash
66	 * device with correct parameters. This config option is board-specific.
67	 */
68	.org 0x10
69	.word CONFIG_SYS_XWAY_EBU_BOOTCFG
70	.word 0x0
71#endif
72#if defined(CONFIG_MALTA)
73	/*
74	 * Linux expects the Board ID here.
75	 */
76	.org 0x10
77	.word 0x00000420	# 0x420 (Malta Board with CoreLV)
78	.word 0x00000000
79#endif
80
81#if defined(CONFIG_ROM_EXCEPTION_VECTORS)
82	.org 0x200
83	/* TLB refill, 32 bit task */
841:	b	1b
85	 nop
86
87	.org 0x280
88	/* XTLB refill, 64 bit task */
891:	b	1b
90	 nop
91
92	.org 0x300
93	/* Cache error exception */
941:	b	1b
95	 nop
96
97	.org 0x380
98	/* General exception */
991:	b	1b
100	 nop
101
102	.org 0x400
103	/* Catch interrupt exceptions */
1041:	b	1b
105	 nop
106
107	.org 0x480
108	/* EJTAG debug exception */
1091:	b	1b
110	 nop
111
112	.org 0x500
113#endif
114
115reset:
116#if __mips_isa_rev >= 6
117	mfc0	t0, CP0_CONFIG, 5
118	and	t0, t0, MIPS_CONF5_VP
119	beqz	t0, 1f
120	 nop
121
122	b	2f
123	 mfc0	t0, CP0_GLOBALNUMBER
124#endif
125
1261:	mfc0	t0, CP0_EBASE
127	and	t0, t0, EBASE_CPUNUM
128
129	/* Hang if this isn't the first CPU in the system */
1302:	beqz	t0, 4f
131	 nop
1323:	wait
133	b	3b
134	 nop
135
136	/* Clear watch registers */
1374:	MTC0	zero, CP0_WATCHLO
138	mtc0	zero, CP0_WATCHHI
139
140	/* WP(Watch Pending), SW0/1 should be cleared */
141	mtc0	zero, CP0_CAUSE
142
143	setup_c0_status STATUS_SET 0
144
145	/* Init Timer */
146	mtc0	zero, CP0_COUNT
147	mtc0	zero, CP0_COMPARE
148
149#ifndef CONFIG_SKIP_LOWLEVEL_INIT
150	mfc0	t0, CP0_CONFIG
151	and	t0, t0, MIPS_CONF_IMPL
152	or	t0, t0, CONF_CM_UNCACHED
153	mtc0	t0, CP0_CONFIG
154	ehb
155#endif
156
157	/*
158	 * Initialize $gp, force pointer sized alignment of bal instruction to
159	 * forbid the compiler to put nop's between bal and _gp. This is
160	 * required to keep _gp and ra aligned to 8 byte.
161	 */
162	.align	PTRLOG
163	bal	1f
164	 nop
165	PTR	_gp
1661:
167	PTR_L	gp, 0(ra)
168
169#ifdef CONFIG_MIPS_CM
170	PTR_LA	t9, mips_cm_map
171	jalr	t9
172	 nop
173#endif
174
175#ifndef CONFIG_SKIP_LOWLEVEL_INIT
176# ifdef CONFIG_SYS_MIPS_CACHE_INIT_RAM_LOAD
177	/* Initialize any external memory */
178	PTR_LA	t9, lowlevel_init
179	jalr	t9
180	 nop
181# endif
182
183	/* Initialize caches... */
184	PTR_LA	t9, mips_cache_reset
185	jalr	t9
186	 nop
187
188# ifndef CONFIG_SYS_MIPS_CACHE_INIT_RAM_LOAD
189	/* Initialize any external memory */
190	PTR_LA	t9, lowlevel_init
191	jalr	t9
192	 nop
193# endif
194#endif
195
196	/* Set up temporary stack */
197	li	t0, -16
198	PTR_LI	t1, CONFIG_SYS_INIT_SP_ADDR
199	and	sp, t1, t0		# force 16 byte alignment
200	PTR_SUBU \
201		sp, sp, GD_SIZE		# reserve space for gd
202	and	sp, sp, t0		# force 16 byte alignment
203	move	k0, sp			# save gd pointer
204#ifdef CONFIG_SYS_MALLOC_F_LEN
205	li	t2, CONFIG_SYS_MALLOC_F_LEN
206	PTR_SUBU \
207		sp, sp, t2		# reserve space for early malloc
208	and	sp, sp, t0		# force 16 byte alignment
209#endif
210	move	fp, sp
211
212	/* Clear gd */
213	move	t0, k0
2141:
215	PTR_S	zero, 0(t0)
216	blt	t0, t1, 1b
217	 PTR_ADDIU t0, PTRSIZE
218
219#ifdef CONFIG_SYS_MALLOC_F_LEN
220	PTR_S	sp, GD_MALLOC_BASE(k0)	# gd->malloc_base offset
221#endif
222
223	move	a0, zero		# a0 <-- boot_flags = 0
224	PTR_LA	t9, board_init_f
225	jr	t9
226	 move	ra, zero
227
228	END(_start)
229
230/*
231 * void relocate_code (addr_sp, gd, addr_moni)
232 *
233 * This "function" does not return, instead it continues in RAM
234 * after relocating the monitor code.
235 *
236 * a0 = addr_sp
237 * a1 = gd
238 * a2 = destination address
239 */
240ENTRY(relocate_code)
241	move	sp, a0			# set new stack pointer
242	move	fp, sp
243
244	move	s0, a1			# save gd in s0
245	move	s2, a2			# save destination address in s2
246
247	PTR_LI	t0, CONFIG_SYS_MONITOR_BASE
248	PTR_SUB	s1, s2, t0		# s1 <-- relocation offset
249
250	PTR_LA	t2, __image_copy_end
251	move	t1, a2
252
253	/*
254	 * t0 = source address
255	 * t1 = target address
256	 * t2 = source end address
257	 */
2581:
259	PTR_L	t3, 0(t0)
260	PTR_S	t3, 0(t1)
261	PTR_ADDU t0, PTRSIZE
262	blt	t0, t2, 1b
263	 PTR_ADDU t1, PTRSIZE
264
265	/*
266	 * Now we want to update GOT.
267	 *
268	 * GOT[0] is reserved. GOT[1] is also reserved for the dynamic object
269	 * generated by GNU ld. Skip these reserved entries from relocation.
270	 */
271	PTR_LA	t3, num_got_entries
272	PTR_LA	t8, _GLOBAL_OFFSET_TABLE_
273	PTR_ADD	t8, s1			# t8 now holds relocated _G_O_T_
274	PTR_ADDIU t8, t8, 2 * PTRSIZE	# skipping first two entries
275	PTR_LI	t2, 2
2761:
277	PTR_L	t1, 0(t8)
278	beqz	t1, 2f
279	 PTR_ADD t1, s1
280	PTR_S	t1, 0(t8)
2812:
282	PTR_ADDIU t2, 1
283	blt	t2, t3, 1b
284	 PTR_ADDIU t8, PTRSIZE
285
286	/* Update dynamic relocations */
287	PTR_LA	t1, __rel_dyn_start
288	PTR_LA	t2, __rel_dyn_end
289
290	b	2f			# skip first reserved entry
291	 PTR_ADDIU t1, 2 * PTRSIZE
292
2931:
294	lw	t8, -4(t1)		# t8 <-- relocation info
295
296	PTR_LI	t3, MIPS_RELOC
297	bne	t8, t3, 2f		# skip non-MIPS_RELOC entries
298	 nop
299
300	PTR_L	t3, -(2 * PTRSIZE)(t1)	# t3 <-- location to fix up in FLASH
301
302	PTR_L	t8, 0(t3)		# t8 <-- original pointer
303	PTR_ADD	t8, s1			# t8 <-- adjusted pointer
304
305	PTR_ADD	t3, s1			# t3 <-- location to fix up in RAM
306	PTR_S	t8, 0(t3)
307
3082:
309	blt	t1, t2, 1b
310	 PTR_ADDIU t1, 2 * PTRSIZE	# each rel.dyn entry is 2*PTRSIZE bytes
311
312	/*
313	 * Flush caches to ensure our newly modified instructions are visible
314	 * to the instruction cache. We're still running with the old GOT, so
315	 * apply the reloc offset to the start address.
316	 */
317	PTR_LA	a0, __text_start
318	PTR_LA	a1, __text_end
319	PTR_SUB	a1, a1, a0
320	PTR_LA	t9, flush_cache
321	jalr	t9
322	 PTR_ADD	a0, s1
323
324	PTR_ADD	gp, s1			# adjust gp
325
326	/*
327	 * Clear BSS
328	 *
329	 * GOT is now relocated. Thus __bss_start and __bss_end can be
330	 * accessed directly via $gp.
331	 */
332	PTR_LA	t1, __bss_start		# t1 <-- __bss_start
333	PTR_LA	t2, __bss_end		# t2 <-- __bss_end
334
3351:
336	PTR_S	zero, 0(t1)
337	blt	t1, t2, 1b
338	 PTR_ADDIU t1, PTRSIZE
339
340	move	a0, s0			# a0 <-- gd
341	move	a1, s2
342	PTR_LA	t9, board_init_r
343	jr	t9
344	 move	ra, zero
345
346	END(relocate_code)
347